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| 型號： | PC8641MSH1333JB |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, CBGA1023 |
| 封裝： | 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023 |
| 文件頁數(shù)： | 40/111頁 |
| 文件大小： | 1660K |
| 代理商： | PC8641MSH1333JB |
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34
0893C–HIREL–01/10
PC8641 and PC8641D [Preliminary]
e2v semiconductors SAS 2010
9.2.4.2
TBI Receive AC Timing Specifications
Table 9-10 provides the TBI receive AC timing specifications.
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t
(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTRDVKH symbolizes TBI receive timing
(TR) with respect to the time data input signals (D) reach the valid state (V) relative to the tTRX clock reference (K) going to
the high (H) state or setup time. Also, t
TRDXKH symbolizes TBI receive timing (TR) with respect to the time data input signals
(D) went invalid (X) relative to the t
TRX clock reference (K) going to the high (H) state. Note that, in general, the clock refer-
ence symbol representation is based on three letters representing the clock of a particular functional. For example, the
subscript of t
TRX represents the TBI (T) receive (RX) clock. For rise and fall times, the latter convention is used with the
appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that is
being skewed (TRX).
2. Guaranteed by design.
Figure 9-10 shows the TBI receive AC timing diagram.
Figure 9-10. TBI Receive AC Timing Diagram
Table 9-10.
TBI Receive AC Timing Specifications (At Recommended Operating Conditions with L/TV
DD of 3.3V ± 5%
and 2.5V ± 5%)
Parameter/Condition
Symbol(1)
Min
Typ
Max
Unit
PMA_RX_CLK[0:1] clock period
tTRX
–
16.0
–
ns
PMA_RX_CLK[0:1] skew
t
SKTRX
7.5
–
8.5
ns
PMA_RX_CLK[0:1] duty cycle
t
TRXH/tTRX
40
–
60
%
RCG[9:0] setup time to rising PMA_RX_CLK
tTRDVKH
2.5
–
ns
RCG[9:0] hold time to rising PMA_RX_CLK
t
TRDXKH
1.5
–
ns
PMA_RX_CLK[0:1] clock rise time (20%-80%)
t
TRXR
0.7
–
2.4
ns
PMA_RX_CLK[0:1] clock fall time (80%-20%)
tTRXF
0.7
–
2.4
ns
Valid Data
PMA_RX_CLK1
RCG[9:0]
tTRXH
tTRXR
tTRXF
tTRDVKH
PMA_RX_CLK0
tTRDXKH
tTRDVKH
tTRDXKH
tSKTRX
tTRXH
tTRX
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