參數(shù)資料
型號： PC8641MSH1333JB
廠商： E2V TECHNOLOGIES PLC
元件分類： 微控制器/微處理器
英文描述： MICROPROCESSOR, CBGA1023
封裝： 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023
文件頁數(shù)： 27/111頁
文件大小： 1660K
代理商： PC8641MSH1333JB
22
0893C–HIREL–01/10
PC8641 and PC8641D [Preliminary]
e2v semiconductors SAS 2010
7.2.2
DDR SDRAM Output AC Timing Specifications
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD) from the
rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, t
DDKHAS symbol-
izes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are setup
(S) or output valid time. Also, t
DDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes low (L)
until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.
Table 7-9.
DDR SDRAM Output AC Timing Specifications (At Recommended Operating Conditions)
Parameter
Symbol(1)
Min
Max
Unit
Notes
MCK[n] cycle time, MCK[n]/MCK[n] crossing
t
MCK
310
ns
MCK duty cycle
600 MHz
533 MHz
400 MHz
tMCKH/tMCK
47.5
47
52.5
53
%
ADDR/CMD output setup with respect to MCK
600 MHz
533 MHz
400 MHz
t
DDKHAS
1.10
1.48
1.95
–
ns
ADDR/CMD output hold with respect to MCK
600 MHz
533 MHz
400 MHz
t
DDKHAX
1.10
1.48
1.95
–
ns
MCS[n] output setup with respect to MCK
600 MHz
533 MHz
400 MHz
tDDKHCS
1.10
1.48
1.95
–
ns
MCS[n] output hold with respect to MCK
600 MHz
533 MHz
400 MHz
t
DDKHCX
1.10
1.48
1.95
–
ns
MCK to MDQS Skew
tDDKHMH
-0.6
0.6
ns
MDQ/MECC/MDM output setup with respect to MDQS
600 MHz
533 MHz
400 MHz
tDDKHDS,
tDDKLDS
500
590
700
–
ps
MDQ/MECC/MDM output hold with respect to MDQS
600 MHz
533 MHz
400 MHz
tDDKHDX,
tDDKLDX
500
590
700
–
ps
MDQS preamble start
tDDKHMP
-0.5 × tMCK – 0.6
-0.5 x tMCK +0.6
ns
MDQS epilogue end
t
DDKHME
-0.6
0.6
ns
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