參數(shù)資料
型號(hào)： PC8641MSH1333JB
廠商： E2V TECHNOLOGIES PLC
元件分類： 微控制器/微處理器
英文描述： MICROPROCESSOR, CBGA1023
封裝： 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023
文件頁數(shù)： 21/111頁
文件大小： 1660K
代理商： PC8641MSH1333JB
17
0893C–HIREL–01/10
e2v semiconductors SAS 2010
PC8641 and PC8641D [Preliminary]
Note:
The phase between the output clocks TSEC1_GTX_CLK and TSEC2_GTX_CLK (ports 1 and 2) is no more
than 100 ps. The phase between the output clocks TSEC3_GTX_CLK and TSEC4_GTX_CLK (ports 3 and
4) is no more than 100 ps.
5.4
Platform Frequency Requirements for PCI-Express and Serial RapidIO
The MPX platform clock frequency must be considered for proper operation of the high-speed PCI
Express and Serial RapidIO interfaces as described below.
For proper PCI Express operation, the MPX clock frequency must be greater than or equal to:
Note that at MPX = 400 MHz, cfg_plat_freq = 0 and at MPX > 400 MHz, cfg_plat_freq = 1. Therefore,
when operating PCI Express in x8 link width, the MPX platform frequency must be 400 MHz with
cfg_plat_freq = 0 or greater than or equal to 527 MHz with cfg_plat_freq = 1.
For proper Serial RapidIO operation, the MPX clock frequency must be greater than:
5.5
Other Input Clocks
For information on the input clocks of other functional blocks of the platform such as SerDes, and
eTSEC, see the specific section of this document.
6.
RESET Initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements of
the PC8641. Table 6-1 provides the RESET initialization AC timing specifications for the DDR SDRAM
component(s).
Notes:
1. SYSCLK is the primary clock input for the PC8641.
2. This is related to HRESET assertion time. Stable PLL configuration inputs are required when a stable SYSCLK is applied.
See the PC8641D Integrated Host Processor Reference Manual for more details on the power-on reset sequence.
527 MHz
(PCI-Express link width)
×
16 / (1 + cfg_plat_freq)
-----------------------------------------------------------------------------------------------
2
(0.80)
×
(Serial RapidIO interface frequency)
×
(Serial RapidIO link width)
×
64
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Table 6-1.
RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HRESET
100
–
s
Minimum assertion time for SRESET_0 & SRESET_1
3
–
SYSCLKs
Platform PLL input setup time with stable SYSCLK before HRESET
negation
100
–
s
Input setup time for POR configs (other than PLL config) with
respect to negation of HRESET
4
–
SYSCLKs
Input hold time for all POR configs (including PLL config) with
respect to negation of HRESET
2
–
SYSCLKs
Maximum valid-to-high impedance time for actively driven POR
configs with respect to negation of HRESET
–
5
SYSCLKs
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