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| 型號(hào)： | PC8641MSH1333JB |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, CBGA1023 |
| 封裝： | 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023 |
| 文件頁數(shù)： | 28/111頁 |
| 文件大小： | 1660K |
| 代理商： | PC8641MSH1333JB |
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23
0893C–HIREL–01/10
e2v semiconductors SAS 2010
PC8641 and PC8641D [Preliminary]
4. Note that t
DDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD)
from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control
of the DQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This will typically be set to the same
delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parame-
ters have been set to the same adjustment value. See the PC8641 Integrated Processor Reference Manual for a description and
understanding of the timing modifications enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that t
DDKHMP follows the sym-
bol conventions described in note 1.
7. Maximum DDR1 frequency is 400 MHz.
8. Per the JEDEC spec the DDR2 duty cycle at 600 MHz is the average low and high cycle time values that are defined as the
average pulse widths calculated across any consecutive 200 pulses. Jitter can sometimes force single low and high cycle
times to drift from the average values. tJIT = ±125 ps.
9. Per the JEDEC spec the DDR2 duty cycle at 400 and 533 MHz is the low and high cycle time values.
Note:
For the ADDR/CMD setup and hold specifications in Table 7-9 on page 22, it is assumed that the clock con-
trol register is set to adjust the memory clocks by 1/2 applied cycle.
Figure 7-1 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (t
DDKHMH).
Figure 7-1.
Timing Diagram for t
DDKHMH
MDQS
MCK[n]
tMCK
MDQS
tDDKHMH(max) = 0.6 ns
tDDKHMH(min) = -0.6 ns
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