參數(shù)資料
型號： PC8641MSH1333JB
廠商： E2V TECHNOLOGIES PLC
元件分類： 微控制器/微處理器
英文描述： MICROPROCESSOR, CBGA1023
封裝： 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023
文件頁數(shù)： 19/111頁
文件大小： 1660K
代理商： PC8641MSH1333JB
15
0893C–HIREL–01/10
e2v semiconductors SAS 2010
PC8641 and PC8641D [Preliminary]
5.
Input Clocks
Table 5-1 provides the system clock (SYSCLK) DC specifications for the PC8641.
Note:
1. Note that the symbol OV
IN, in this case, represents the OVIN symbol referenced in Table 3-1 on page 6
5.1
System Clock Timing
Table 5-2 provides the system clock (SYSCLK) AC timing specifications for the PC8641.
Notes:
1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting
SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum
PLL Ratio” on page 88, for ratio settings.
2. Rise and fall times for SYSCLK are measured at 0.4V and 2.7V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter: short term and long term, and is guaranteed by design.
5. The SYSCLK driver’s closed loop jitter bandwidth should be < 500 kHz at -20 dB. The bandwidth must be set low to allow
cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter. Note that the frequency modulation
for SYSCLK reduces significantly for the spread spectrum source case. This is to guarantee what is supported based on
design.
5.1.1
SYSCLK and Spread Spectrum Sources
Spread spectrum clock sources are an increasingly popular way to control electromagnetic interference
emissions (EMI) by spreading the emitted noise to a wider spectrum and reducing the peak noise magni-
tude in order to meet industry and government requirements. These clock sources intentionally add long-
term jitter in order to diffuse the EMI spectral content. The jitter specification given in Table 5-3 considers
short-term (cycle-to-cycle) jitter only and the clock generator’s cycle-to-cycle output jitter should meet the
PC8641 input cycle-to-cycle jitter requirement. Frequency modulation and spread are separate con-
Table 5-1.
SYSCLK DC Electrical Characteristics (OV
DD = 3.3V ± 165 mV)
Parameter
Symbol
Min
Max
Unit
High-level input voltage
V
IH
2OV
DD + 0.3
V
Low-level input voltage
V
IL
-0.3
0.8
V
Input current
(V
IN
(1) = 0V or V
IN = VDD)
I
IN
–±5
A
Table 5-2.
SYSCLK AC Timing Specifications
(At Recommended Operating Conditions with OV
DD = 3.3V ± 165 mV. See Table 3-2 on page 7)
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
SYSCLK frequency
f
SYSCLK
66
–
166.66
MHz
SYSCLK cycle time
t
SYSCLK
6––
ns
–
SYSCLK rise and fall time
tKH, tKL
0.6
1.0
1.2
ns
SYSCLK duty cycle
t
KHK/tSYSCLK
40
60
%
SYSCLK jitter
–
150
ps
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