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參數(shù)資料
| 型號： | PC8641MSH1333JB |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, CBGA1023 |
| 封裝： | 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023 |
| 文件頁數(shù)： | 23/111頁 |
| 文件大?。?/td> | 1660K |
| 代理商： | PC8641MSH1333JB |
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19
0893C–HIREL–01/10
e2v semiconductors SAS 2010
PC8641 and PC8641D [Preliminary]
4. Output leakage is measured with all outputs disabled, 0V
≤V
OUT ≤Dn_GVDD.
Table 7-2 provides the DDR capacitance when GV
DD (typ) = 1.8V.
Note:
1. This parameter is sampled.Dn_ GVDD = 1.8V ± 0.090V, f = 1 MHz, TA = 25° C, VOUT = Dn_GVDD/2, VOUT
(peak-to-peak) = 0.2V.
Table 7-3 provides the recommended operating conditions for the DDR SDRAM component(s) when
Dn_GV
DD(typ) = 2.5V.
Notes:
1. Dn_GV
DD is expected to be within 50 mV of the DRAM Dn_GVDD at all times.
2. MVREF is expected to be equal to 0.5 × Dn_GVDD, and to track Dn_GVDD DC variations as measured at the receiver. Peak-to-
peak noise on Dn_MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to Dn_MVREF. This rail should track variations in the DC level of Dn_MVREF.
4. Output leakage is measured with all outputs disabled, 0V
≤V
OUT ≤GVDD.
Table 7-4 provides the DDR capacitance when Dn_GV
DD (typ) = 2.5V.
Note:
1. This parameter is sampled. Dn_GVDD = 2.5V ± 0.125V, f = 1 MHz, TA = 25° C, VOUT = Dn_GVDD/2, VOUT (peak-to-peak)
=0.2V.
Table 7-2.
DDR2 SDRAM Capacitance for Dn_GV
DD(typ) = 1.8V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS, DQS
C
IO
68
pF
Delta input/output capacitance: DQ, DQS, DQS
CDIO
–0.5
pF
Table 7-3.
DDR SDRAM DC Electrical Characteristics for Dn_GV
DD (typ) = 2.5V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
I/O supply voltage
Dn_GV
DD
2.375
2.625
V
I/O reference voltage
Dn_MVREF
0.49 × Dn_GVDD
0.51 × Dn_GVDD
V
I/O termination voltage
V
TT
Dn_MV
REF – 0.04
Dn_MV
REF + 0.04
V
Input high voltage
V
IH
Dn_MV
REF + 0.15
Dn_GV
DD + 0.3
V
Input low voltage
VIL
-0.3
Dn_MVREF – 0.15
V
Output leakage current
I
OZ
-9.9
9.9
A
Output high current (VOUT = 1.95V)
IOH
-16.2
–
mA
Output low current (VOUT = 0.35V)
IOL
16.2
–
mA
Table 7-4.
DDR SDRAM Capacitance for Dn_GV
DD (typ) = 2.5V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS
CIO
68
pF
Delta input/output capacitance: DQ, DQS
C
DIO
–0.5
pF
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