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參數(shù)資料
| 型號： | PC8641MSH1333JB |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, CBGA1023 |
| 封裝： | 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023 |
| 文件頁數(shù)： | 2/111頁 |
| 文件大小： | 1660K |
| 代理商： | PC8641MSH1333JB |
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10
0893C–HIREL–01/10
PC8641 and PC8641D [Preliminary]
e2v semiconductors SAS 2010
3.2
Power Up/Down Sequence
The PC8641 requires its power rails to be applied in a specific sequence in order to ensure proper
device operation.
Note:
The recommended maximum ramp up time for power supplies is 20 milliseconds.
The chronological order of power up is:
1.
All power rails other than DDR I/O (Dn_GV
DD, and Dn_MVREF).
Note:
There is no required order sequence between the individual rails for this item (# 1). However, VDD_PLAT,
AV
DD_PLAT rails must reach 90% of their recommended value before the rail for Dn_GVDD, and Dn_MVREF
(in next step) reaches 10% of their recommended value. AV
DD type supplies must be delayed with respect
to their source supplies by the RC time constant of the PLL filter circuit described in Section 21.2.1 ”PLL
2.
Dn_GV
DD, Dn_MVREF
Note:
It is possible to leave the related power supply (Dn_GV
DD, Dn_MVREF) turned off at reset for a DDR port
that will not be used. Note that these power supplies can only be powered up again at reset for functionality
to occur on the DDR port.
3.
SYSCLK
The recommended order of power down is as follows:
1.
Dn_GV
DD, Dn_MVREF
2.
All power rails other than DDR I/O (Dn_GV
DD, Dn_MVREF).
Note:
SYSCLK may be powered down simultaneous to either of item # 1 or # 2 in the power down sequence.
Beyond this, the power supplies may power down simultaneously if the preservation of DDRn memory is
not a concern.
See Figure 3-2 on page 11 for more details on the Power and Reset Sequencing details.
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