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參數(shù)資料
| 型號： | PC8641MSH1333JB |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, CBGA1023 |
| 封裝： | 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023 |
| 文件頁數(shù)： | 44/111頁 |
| 文件大?。?/td> | 1660K |
| 代理商： | PC8641MSH1333JB |
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38
0893C–HIREL–01/10
PC8641 and PC8641D [Preliminary]
e2v semiconductors SAS 2010
9.2.7.2
RMII Receive AC Timing Specifications
Note:
1. The symbols used for timing specificationsherein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing
(MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
MRX clock reference (K) going to
the high (H) state or setup time. Also, t
MRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals
(D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the
clock reference symbol representation is based on three letters representing the clock of a particular functional. For exam-
ple, the subscript of t
MRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with
the appropriate letter: R (rise) or F (fall).
Figure 9-14 provides the AC test load for eTSEC.
Figure 9-14. eTSEC AC Test Load
Figure 9-15 shows the RMII receive AC timing diagram.
Figure 9-15. RMII Receive AC Timing Diagram
Table 9-14.
RMII Receive AC Timing Specifications (At Recommended Operating Conditions with L/TV
DD of 3.3V ± 5%
and 2.5V ± 5%)
Parameter/Condition
Min
Typ
Max
Unit
Input low voltage at 3.3 OV
DD
V
IL
––
0.8
V
Input high voltage at 3.3 OVDD
VIH
2.0
–
V
REF_CLK clock period
t
RMR
15.0
20.0
25.0
ns
REF_CLK duty cycle
t
RMRH/tRMR
35
50
65
%
REF_CLK peak-to-peak jitter
tRMRJ
––
250
ps
Rise time REF_CLK (20%–80%)
t
RMRR
1.0
–
2.0
ns
Fall time REF_CLK (80%–20%)
t
RMRF
1.0
–
2.0
ns
RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK rising edge
tRMRDV
4.0
–
ns
RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK rising edge
t
RMRDX
2.0
–
ns
LV
DD/2
Output
Z0 = 50Ω
R
L = 50Ω
REF_CLK
RXD[1:0]
tRMRDX
tRMR
tRMRH
tRMRR
tRMRF
CRS_DV
RX_ER
tRMRDV
Valid Data
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