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參數(shù)資料
| 型號： | PC8641MSH1333JB |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, CBGA1023 |
| 封裝： | 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023 |
| 文件頁數(shù)： | 97/111頁 |
| 文件大?。?/td> | 1660K |
| 代理商： | PC8641MSH1333JB |
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86
0893C–HIREL–01/10
PC8641 and PC8641D [Preliminary]
e2v semiconductors SAS 2010
Special Notes for Single Core Device:
S1. Solder ball for this signal will not be populated in the single core package.
S2. The PLL filter from VDD_Core1 to AVDD_Core1 should be removed. AVDD_Core1 should be pulled to ground with a weak (2–10 kΩ)
resistor. See Section 21.2.1 ”PLL Power Supply Filtering” on page 96 for more details.
S3. This pin should be pulled to GND for the single core device.
S4. No special requirement for this pin on single core device. Pin should be tied to power supply as directed for dual core.
19. Clocking
This section describes the PLL configuration of the PC8641. Note that the platform clock is identical to
the MPX clock.
19.1
Clock Ranges
Table 19-1 provides the clocking specifications for the processor cores and Table 19-2 provides the
clocking specifications for the memory bus.
Notes:
1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting
SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to Section 19.2 ”MPX to SYSCLK PLL Ratio” on page 87 and Section 19.3 ”e600 to MPX clock
PLL Ratio” on page 88, for ratio settings.
2. The minimum e600 core frequency is based on the minimum platform clock frequency of 400 MHz.
Notes:
1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting
SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to Section 19.2 ”MPX to SYSCLK PLL Ratio” on page 87.
2. The memory bus clock speed is half the DDR/DDR2 data rate, hence, half the MPX clock frequency.
Table 19-1.
Processor Core Clocking Specifications
Characteristic
Maximum Processor Core Frequency
Unit
Notes
1000 MHz
1250 MHz
1333 MHz
1500 MHz
Min
Max
Min
Max
Min
Max
Min
Max
e500 core processor frequency
800
1000
800
1250
800
1333
800
1500
MHz
Table 19-2.
Memory Bus Clocking Specifications
Characteristic
Maximum Processor Core Frequency
Unit
Notes
1000, 1250, 1333, 1500 MHz
Min
Max
Memory bus clock frequency
200
300
MHz
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