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參數(shù)資料
| 型號(hào)： | PC8641MSH1333JB |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, CBGA1023 |
| 封裝： | 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023 |
| 文件頁數(shù)： | 61/111頁 |
| 文件大?。?/td> | 1660K |
| 代理商： | PC8641MSH1333JB |
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53
0893C–HIREL–01/10
e2v semiconductors SAS 2010
PC8641 and PC8641D [Preliminary]
13.2
I
2C AC Electrical Specifications
Table 13-2 provides the AC timing parameters for the I
2C interfaces.
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I
2C timing (I2) with
respect to the time data input signals (D) reach the valid state (V) relative to the t
I2C clock reference (K) going to the high (H)
state or setup time. Also, tI2SXKL symbolizes I
2C timing (I2) for the time that the data with respect to the start condition (S)
went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I
2C tim-
ing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the t
I2C clock
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropri-
ate letter: R (rise) or F (fall).
2. As a transmitter, the PC8641 provides a delay time of at least 300 ns for the SDA signal (referred to the Vihmin of the SCL
signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition.
When PC8641 acts as the I2C bus master while transmitting, PC8641 drives both SCL and SDA. As long as the load on SCL
and SDA are balanced, PC8641 would not cause unintended generation of Start or Stop condition. Therefore, the 300 ns
SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required for
PC8641 as transmitter, the following setting is recommended for the FDR bit field of the I2CFDR register to ensure both the
desired I2C SCL clock frequency and SDA output delay time are achieved, assuming that the desired I2C SCL clock fre-
quency is 400 KHz and the Digital Filter Sampling Rate Register (I2CDFSRR) is programmed with its default setting of 0x10
(decimal 16):
I2C Source Clock Frequency
333 MHz
266 MHz
200 MHz
133 MHz
FDR Bit Setting
0x2A
0x05
0x26
0x00
Actual FDR Divider Selected
896
704
512
384
Actual I2C SCL Frequency Generated
371 KHz
378 KHz
390 KHz
346 KHz
For the detail of I2C frequency calculation, refer to the application note AN2919 “Determining the I2C Frequency
Divider Ratio for SCL”. Note that the I2C Source Clock Frequency is half of the MPX clock frequency for PC8641.
3. The maximum t
I2DVKH has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.
4. Guaranteed by design.
Table 13-2.
I
2C AC Electrical Specifications (All Values Refer to V
52)
Parameter
Symbol
Min
Max
Unit
SCL clock frequency
f
I2C
0
400
kHz
Low period of the SCL clock
t
1.3
–
s
High period of the SCL clock
t
0.6
–
s
Setup time for a repeated START condition
t
I2SVKH
0.6
–
s
Hold time (repeated) START condition (after this period, the first clock
pulse is generated)
t
I2SXKL
0.6
–
s
Data setup time
t
I2DVKH
100
–
ns
Data input hold time:
- CBUS compatible masters
- I2C bus devices
t
I2DXKL
–
–
s
Data output delay time
t
I2OVKL
–0.9
s
Set-up time for STOP condition
t
I2PVKH
0.6
–
s
Bus free time between a STOP and START condition
t
I2KHDX
1.3
s
Noise margin at the LOW level for each connected device (including
hysteresis)
V
NL
0.1 × OV
DD
V
Noise margin at the HIGH level for each connected device (including
hysteresis)
V
NH
0.2 × OV
DD
V
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