參數(shù)資料
型號： PC8641MSH1333JB
廠商： E2V TECHNOLOGIES PLC
元件分類： 微控制器/微處理器
英文描述： MICROPROCESSOR, CBGA1023
封裝： 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023
文件頁數(shù)： 20/111頁
文件大?。?/td> 1660K
代理商： PC8641MSH1333JB
16
0893C–HIREL–01/10
PC8641 and PC8641D [Preliminary]
e2v semiconductors SAS 2010
cerns, and the PC8641 is compatible with spread spectrum sources if the recommendations listed in
Table 5-3 are observed.
Notes:
1. Guaranteed by design.
2. SYSCLK frequencies resulting from frequency spreading, and the resulting core and VCO frequencies,
must meet the minimum and maximum specifications given in Table 5-3.
It is imperative to note that the processor’s minimum and maximum SYSCLK, core, and VCO frequen-
cies must not be exceeded regardless of the type of clock source. Therefore, systems in which the
processor is operated at its maximum rated e600 core frequency should avoid violating the stated limits
by using down-spreading only.
SDn_REF_CLK and SDn_REF_CLK was designed to work with a spread spectrum clock (+0 to 0.5%
spreading at 30-33kHz rate is allowed), assuming both ends have same reference clock. For better
results use a source without significant unintended modulation.
5.2
Real Time Clock Timing
The RTC input is sampled by the platform clock (MPX clock). The output of the sampling latch is then
used as an input to the counters of the PIC. There is no jitter specification. The minimum pulse width of
the RTC signal should be greater than 2x the period of the MPX clock. That is, minimum clock high time
is 2 × t
MPX, and minimum clock low time is 2 × tMPX. There is no minimum RTC frequency; RTC may be
grounded if not needed.
5.3
eTSEC Gigabit Reference Clock Timing
Table 5-4 provides the eTSEC gigabit reference clocks (EC_1_GTX_CLK125 and EC_2_GTX_CLK125)
AC timing specifications for the PC8641.
Notes:
1. Timing is guaranteed by design and characterization.
2. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. EC_GTX_CLK125
duty cycle can be loosened from 47/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC
100Base-T reference clock.
Table 5-3.
Spread Spectrum Clock Source Recommendations
(At Recommended Operating Conditions. See Table 3-2 on page 7)
Parameter
Min
Max
Unit
Notes
Frequency modulation
–
50
kHz
Frequency spread
–
1.0
%
Table 5-4.
EC_GTX_CLK125 AC Timing Specifications
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
ECn_GTX_CLK125 frequency
f
G125
–125
–
MHz
ECn_GTX_CLK125 cycle time
tG125
–8–
ns
EC_GTX_CLK125 duty cycle
- GMII, TBI
- 1000Base-T for RGMII, RTBI
tG125H/tG125
45
47
–55
53
%
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