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| 型號： | PC8641MSH1333JB |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, CBGA1023 |
| 封裝： | 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023 |
| 文件頁數(shù)： | 65/111頁 |
| 文件大?。?/td> | 1660K |
| 代理商： | PC8641MSH1333JB |
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57
0893C–HIREL–01/10
e2v semiconductors SAS 2010
PC8641 and PC8641D [Preliminary]
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 15-3 on page 61 and
measured over any 250 consecutive TX UIs. (Also refer to the transmitter compliance eye diagram shown in Figure 15-1 on
3. A T
TX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.30 UI for the Trans-
mitter collected over any 250 consecutive TX UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total TX jitter
budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter
median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the
averaged time value.
4. The Transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a common mode
return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement
applies to all valid input levels. The reference impedance for return loss measurements is 50
Ω to ground for both the D+ and
D- line (that is, as measured by a Vector Network Analyzer with 50
Ω probes; see Figure 15-3 on page 61). Note that the
series capacitors C
TX is optional for the return loss measurement.
5. Measured between 20-80% at transmitter package pins into a test load as shown in Figure 15-3 for both VTX-D+ and VTX-D-.
6. See Section 4.3.1.8 of the PCI Express Base Specifications Rev 1.0a.
7. See Section 4.2.6.3 of the PCI Express Base Specifications Rev 1.0a.
8. PC8641D SerDes transmitter does not have CTX built-in. An external AC Coupling capacitor is required.
T
TX-IDLE-SET-TO-
IDLE
Maximum time to
transition to a valid
Electrical idle after
sending an Electrical Idle
ordered set
20
UI
After sending an Electrical Idle ordered set, the Transmitter
must meet all Electrical Idle Specifications within this time.
This is considered a debounce time for the Transmitter to
meet Electrical Idle after transitioning from LO.
T
TX-IDLE-TO-DIFF-
DATA
Maximum time to
transition to valid TX
specifications after
leaving an Electrical idle
condition
20
UI
Maximum time to meet all TX specifications when
transitioning from Electrical Idle to sending differential data.
This is considered a debounce time for the TX to meet all
TX specifications after leaving Electrical Idle.
RL
TX-DIFF
Differential Return Loss
12
dB
Measured over 50 MHz to 1.25 GHz. See Note
RL
TX-CM
Common Mode Return
Loss
6
dB
Measured over 50 MHz to 1.25 GHz. See Note
Z
TX-DIFF-DC
DC Differential TX
Impedance
80
100
120
Ω
TX DC Differential mode Low Impedance.
Z
TX-DC
Transmitter DC
Impedance
40
Ω
Required TX D+ as wellall states.
L
TX-SKEW
Lane-to-Lane Output
Skew
500 + 2
UI
ps
Static skew between any two Transmitter Lanes within a
single Link.
C
TX
AC Coupling Capacitor
75
200
nF
All Transmitters shall be AC coupled. The AC coupling is
required either within the media or within the transmitting
component itself. See Note(8)
T
crosslink
Crosslink Random
Timeout
01
ms
This random timeout helps resolve conflicts in crosslink
configuration by eventually resulting in only one
Downstream and one Upstream Port. See Note(7).
Table 15-2.
Differential Transmitter (TX) Output Specifications (Continued)
Symbol
Parameter
Min
Nom
Max
Units
Comments
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