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參數(shù)資料
| 型號： | PC8641MSH1333JB |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, CBGA1023 |
| 封裝： | 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023 |
| 文件頁數(shù)： | 111/111頁 |
| 文件大小： | 1660K |
| 代理商： | PC8641MSH1333JB |
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99
0893C–HIREL–01/10
e2v semiconductors SAS 2010
PC8641 and PC8641D [Preliminary]
Notes:
1. Partial Termination when a SerDes port is enabled through both POR input and DEVDISR is deter-
mined by the SerDes port mode. If the port is in x8 PCI Express mode, no termination is required
because all pins are being used. If the port is in x1/x2/x4 PCI Express mode, termination is required on
the unused pins. If the port is in x4 Serial RapidIO mode termination is required on the unused pins.
2. If a SerDes port is enabled through the POR input and then disabled through DEVDISR, no hardware
changes are required. Termination of the SerDes port should follow what is required when the port is
enabled through both POR input and DEVDISR. See Note(1) for more information.
If the high-speed SerDes port requires complete or partial termination, the unused pins should be termi-
nated as described in this section.
The following pins must be left unconnected (floating):
SDn_TX[7:0]
The following pins must be connected to GND:
SDn_RX[7:0]
SDn_REF_CLK
SDn_REF_CLK
Note:
It is recommended to power down the unused lane through SRDS1CR1[0:7] register (offset = 0xE_0F08)
and SRDS2CR1[0:7] register (offset = 0xE_0F44.) (This prevents the oscillations and holds the receiver
output in a fixed state.) that maps to SERDES lane 0 to lane 7 accordingly.
For other directions on reserved or no-connects pins see Section 18. ”Signal Listings” on page 75.
Table 21-1.
SerDes Port Enabled/Disabled Configurations
Disabled through POR input
Enabled through POR input
Enabled through DEVDISR
SerDes port is disabled (and cannot
be enabled through DEVDISR)
Complete termination required
(Reference Clock not required)
SerDes port is enabled
Partial termination may be required(1)
(Reference Clock is required)
Disabled through DEVDISR
SerDes port is disabled (through POR
input)
Complete termination required
(Reference Clock not required)
SerDes port is disabled after software
disables port
Same termination requirements as
when the port is enabled through POR
input(2)
(Reference Clock is required)
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