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參數(shù)資料
| 型號： | PC8641MSH1333JB |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, CBGA1023 |
| 封裝： | 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023 |
| 文件頁數(shù)： | 105/111頁 |
| 文件大?。?/td> | 1660K |
| 代理商： | PC8641MSH1333JB |
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93
0893C–HIREL–01/10
e2v semiconductors SAS 2010
PC8641 and PC8641D [Preliminary]
T
I is the inlet cabinet ambient temperature
T
R is the air temperature rise within the computer cabinet
RθJC is the junction-to-case thermal resistance
RθINT is the adhesive or interface material thermal resistance
RθSA is the heat sink base-to-ambient thermal resistance
P
D is the power dissipated by the device
During operation, the die-junction temperatures (T
J) should be maintained less than the value specified
in Table 3-2 on page 7. The temperature of air cooling the component greatly depends on the ambient
inlet air temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-
air temperature (T
i) may range from 30° to 40° C. The air temperature rise within a cabinet (TR) may be in
the range of 5
° to 10° C. The thermal resistance of the thermal interface material (RθINT) is typically about
0.2
° C/W. For example, assuming a T
I of 30° C, a Tr of 5° C, a package R
θJC = 0.1, and a typical power
consumption (P
D) of 43.4 W, the following expression for T
J is obtained:
Die-junction temperature: T
J = 30° C + 5° C + (0.1° C/W + 0.2° C/W + θsa) × 43.4 W
For this example, a Rθsa value of 1.32° C/W or less is required to maintain the die junction temperature
below the maximum value of Table 3-2.
Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common fig-
ure-of-merit used for comparing the thermal performance of various microelectronic packaging
technologies, one should exercise caution when only using this metric in determining thermal manage-
ment because no single parameter can adequately describe three-dimensional heat flow. The final die-
junction operating temperature is not only a function of the component-level thermal resistance, but the
system-level design and its operating conditions. In addition to the component's power consumption, a
number of factors affect the final operating die-junction temperature—airflow, board population (local
heat flux of adjacent components), heat sink efficiency, heat sink placement, next-level interconnect
technology, system air temperature rise, altitude, and so on.
Due to the complexity and variety of system-level boundary conditions for today's microelectronic equip-
ment, the combined effects of the heat transfer mechanisms (radiation, convection, and conduction) may
vary widely. For these reasons, we recommend using conjugate heat transfer models for the board as
well as system-level designs.
For system thermal modeling, the PC8641 thermal model is shown in Figure 20-5 on page 94. Four
cuboids are used to represent this device. The die is modeled as 12.4x15.3 mm at a thickness of 0.86
mm. See Section 4. ”Power Characteristics” on page 12 for power dissipation details. The substrate is
modeled as a single block 33x33x1.2 mm with orthotropic conductivity: 13.5 W/(m K) in the xy-plane
and 5.3 W/(m K) in the z-direction. The die is centered on the substrate. The bump/underfill layer is
modeled as a collapsed thermal resistance between the die and substrate with a conductivity of 5.3
W/(m K) in the thickness dimension of 0.07 mm. Because the bump/underfill is modeled with zero phys-
ical dimension (collapsed height), the die thickness was slightly enlarged to provide the correct height.
The C5 solder layer is modeled as a cuboid with dimensions 33x33x0.4 mm and orthotropic thermal con-
ductivity of 0.034 W/(m K) in the xy-plane and 9.6 W/(m K) in the z-direction. An LGA solder layer
would be modeled as a collapsed thermal resistance with thermal conductivity of 9.6W/(m K) and an
effective height of 0.1 mm. The thermal model uses approximate dimensions to reduce grid. Please refer
to the case outline for actual dimensions.
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