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參數(shù)資料
| 型號： | PC8641MSH1333JB |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, CBGA1023 |
| 封裝： | 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023 |
| 文件頁數(shù)： | 72/111頁 |
| 文件大?。?/td> | 1660K |
| 代理商： | PC8641MSH1333JB |
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63
0893C–HIREL–01/10
e2v semiconductors SAS 2010
PC8641 and PC8641D [Preliminary]
Figure 16-1. Differential Peak-Peak Voltage of Transmitter or Receiver
To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) trans-
mitter that has a common mode voltage of 2.25V and each of its outputs, TD and TD, has a swing that
goes between 2.5V and 2.0V. Using these values, the peak-to-peak voltage swing of the signals TD and
TD is 500 mV p-p. The differential output signal ranges between 500 mV and –500 mV. The peak differ-
ential voltage is 500 mV. The peak-to-peak differential voltage is 1000 mV p-p.
16.4
Equalization
With the use of high speed serial links, the interconnect media will cause degradation of the signal at the
receiver. Effects such as Inter-Symbol Interference (ISI) or data dependent jitter are produced. This loss
can be large enough to degrade the eye opening at the receiver beyond what is allowed in the
specification.
To negate a portion of these effects, equalization can be used. The most common equalization tech-
niques that can be used are:
A passive high pass filter network placed at the receiver. This is often referred to as passive
equalization.
The use of active circuits in the receiver. This is often referred to as adaptive equalization.
16.5
Explanatory Note on Transmitter and Receiver Specifications
AC electrical specifications are given for transmitter and receiver. Long run and short run interfaces at
three baud rates (a total of six cases) are described.
The parameters for the AC electrical specifications are guided by the XAUI electrical interface specified
in Clause 47 of IEEE 802.3ae-2002.
XAUI has similar application goals to serial RapidIO, as described in Section 9.1 on page 26. The goal of
this standard is that electrical designs for serial RapidIO can reuse electrical designs for XAUI, suitably
modified for applications at the baud intervals and reaches described herein.
A Volts
B Volts
TD or RD
Differential Peak-Peak = 2*(A-B)
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