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| 型號： | PC8641MSH1333JB |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, CBGA1023 |
| 封裝： | 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023 |
| 文件頁數(shù)： | 96/111頁 |
| 文件大小： | 1660K |
| 代理商： | PC8641MSH1333JB |
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85
0893C–HIREL–01/10
e2v semiconductors SAS 2010
PC8641 and PC8641D [Preliminary]
9. This multiplexed pin has input status in one mode and output in another.
10. This pin is a multiplexed signal for different functional blocks and appears more than once in this table.
11. This pin is open drain signal.
12. Functional only on the PC8641D.
13. These pins should be left floating.
14. These pins should be connected to SVDD.
15. These pins should be pulled to ground with a strong resistor (270-
Ωto 330-Ω).
16. These pins should be connected to OVDD.
17. This is a SerDes PLL/DLL digital test signal and is only for factory use.
18. This is a SerDes PLL/DLL analog test signal and is only for factory use.
19. This pin should be pulled to ground with a 100
Ωresistor.
20. The pins in this section are reset configuration pins. Each pin has a weak internal pull-up P-FET which is enabled only when
the processor is in the reset state. This pull-up is designed such that it can be overpowered by an external 4.7-k
Ωpull-down
resistor. However, if the signal is intended to be high after reset, and if there is any device on the net which might pull down
the value of the net at reset, then a pullup or active driver is needed.
21. Should be pulled down at reset if platform frequency is at 400 MHz.
22. These pins require 4.7-k
Ωpull-up or pull-down resistors and must be driven as they are used to determine PLL configuration
ratios at reset.
23. This output is actively driven during reset rather than being tri-stated during reset.
24. hese JTAG pins have weak internal pull-up P-FETs that are always enabled.
25. This pin should NOT be pulled down (or driven low) during reset.
26. These are test signals for factory use only and must be pulled up (100
Ωto 1 kΩ.) to OV
DD for normal machine operation.
27. Dn_MDIC[0] should be connected to ground with an 18
Ωresistor ± 1Ωand Dn_MDIC[1] should be connected Dn_GV
DD.
28. Pin N18 is recommended as a reference point for determining the voltage of V
DD_PLAT and is hence considered as the
VDD_PLAT sensing voltage and is called SENSEVDD_PLAT.
29. Pin P18 is recommended as the ground reference point for SENSEVDD_PLAT and is called SENSEVSS_PLAT.
30. This pin should be pulled to ground with a 200
Ωresistor.
31. These pins are connected to the power/ground planes internally and may be used by the core power supply to improve
tracking and regulation.
32. Must be tied low if unused.
33. These pins may be used as defined functional reset configuration pins in the future. Please include a resistor pull up/down
option to allow flexibility of future designs.
34. Used as serial data output for SRIO 1x/4x link.
35. Used as serial data input for SRIO 1x/4x link.
36. This pin requires an external 4.7 k
Ωpull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is
actively driven.
37. This pin is only an output in FIFO mode when used as Rx Flow Control.
38. This pin functions as cfg_dram_type[0 or 1] at reset and MUST BE VALID BEFORE HRESET ASSERTION in device sleep
mode.
39. Should be pulled to ground if unused (such as in FIFO, MII and RMII modes).
40. See Section 19.4.2 ”Platform to FIFO restrictions” on page 89 for clock speed limitations for this pin when used in FIFO
mode.
41. The phase between the output clocks TSEC1_GTX_CLK and TSEC2_GTX_CLK (ports 1 and 2) is no more than 100 ps.
The phase between the output clocks TSEC3_GTX_CLK and TSEC4_GTX_CLK (ports 3 and 4) is no more than 100 ps.
42. For systems which boot from Local Bus (GPCM)-controlled flash, a pullup on LGPL4 is required.
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| PC8641VGH1333JE | 制造商:e2v technologies 功能描述:PC8641VGH1333JE - Trays |
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