參數(shù)資料
型號(hào)： PC8641MSH1333JB
廠商： E2V TECHNOLOGIES PLC
元件分類(lèi)： 微控制器/微處理器
英文描述： MICROPROCESSOR, CBGA1023
封裝： 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023
文件頁(yè)數(shù)： 108/111頁(yè)
文件大?。?/td> 1660K
代理商： PC8641MSH1333JB
96
0893C–HIREL–01/10
PC8641 and PC8641D [Preliminary]
e2v semiconductors SAS 2010
21.2
Power Supply Design and Sequencing
21.2.1
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide independent filter circuits per PLL power supply as illustrated in Figure 21-2, one to each of the
AV
DD type pins. By providing independent filters to each PLL the opportunity to cause noise injection
from one PLL to the other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AV
DD type pin being supplied to mini-
mize noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the
AV
DD type pin, which is on the periphery of the footprint, without the inductance of vias.
Figure 21-1 and Figure 21-2 show the PLL power supply filter circuits for the platform and cores,
respectively.
Figure 21-1. PC8641 PLL Power Supply Filter Circuit (for platform and Local bus)
Figure 21-2. PC8641 PLL Power Supply Filter Circuit (for cores)
Note:
For single core device the filter circuit (in the dashed box) should be removed and AV
DD_Core1 should be
tied to ground with a weak (2-10 k
Ω) pull-down resistor.
The AV
DD_SRDSn signals provide power for the analog portions of the SerDes PLL. To ensure stability
of the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in
following figure. For maximum effectiveness, the filter circuit is placed as closely as possible to the
AV
DD_SRDSn balls to ensure it filters out as much noise as possible. The ground connection should be
near the AV
DD_SRDSn balls. The 0.003-F capacitor is closest to the balls, followed by the 1-F capaci-
tor, and finally the 1 ohm resistor to the board supply plane. The capacitors are connected from
AV
DD_SRDSn to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant
frequency. All traces should be kept short, wide and direct.
2. 2 F
2.
2 F
GND
10
Ω
VDD_PLAT
AVDD_PLAT, AVDD_LB
Low ESL Surface Mount Capacitors
VDD_Core0/1
A
VDD_Core0/1
2.2 F
GND
Low ESL Surface Mount Capacitors
10
Filter Circuit (should not be used for Single core device)
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