參數(shù)資料
型號(hào)： PC8641MSH1333JB
廠商： E2V TECHNOLOGIES PLC
元件分類： 微控制器/微處理器
英文描述： MICROPROCESSOR, CBGA1023
封裝： 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023
文件頁(yè)數(shù)： 38/111頁(yè)
文件大?。?/td> 1660K
代理商： PC8641MSH1333JB
32
0893C–HIREL–01/10
PC8641 and PC8641D [Preliminary]
e2v semiconductors SAS 2010
9.2.3.2
MII Receive AC Timing Specifications
Table 9-8 provides the MII receive AC timing specifications.
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t
(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing
(MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
MRX clock reference (K) going to
the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals
(D) went invalid (X) relative to the t
MRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the
clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is
used with the appropriate letter: R (rise) or F (fall).
2. Guaranteed by design.
Figure 9-7 provides the AC test load for eTSEC.
Figure 9-7.
eTSEC AC Test Load
Figure 9-8 shows the MII receive AC timing diagram.
Figure 9-8.
MII Receive AC Timing Diagram
Table 9-8.
MII Transmit AC Timing Specifications (At Recommended Operating Conditions with L/TV
DD of 3.3V ± 5%
and 2.5V ± 5%)
Parameter/Condition
Min
Typ
Max
Unit
Input low voltage
VIL
––
0.7
V
Input high voltage
V
IH
1.9
–
V
RX_CLK clock period 10 Mbps
t
MRX
–
400
–
ns
RX_CLK clock period 100 Mbps
tMRX
–40
–
ns
RX_CLK duty cycle
t
MRXH/tMRX
35
–
65
%
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
t
MRDVKH
10
–
ns
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
tMRDXKH
10
–
ns
RX_CLK clock rise (20%-80%)
t
MRXR
1–
4
ns
RX_CLK clock fall time (80%-20%)
t
MRXF
1–
4
ns
LV
DD/2
Output
Z0 = 50Ω
R
L = 50Ω
RX_CLK
RXD[3:0]
tMRDXKL
tMRX
tMRXH
tMRXR
tMRXF
tMRDVKH
RX_DV
RX_ER
Valid Data
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