參數(shù)資料
型號(hào)： PC8641MSH1333JB
廠商： E2V TECHNOLOGIES PLC
元件分類： 微控制器/微處理器
英文描述： MICROPROCESSOR, CBGA1023
封裝： 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023
文件頁數(shù)： 32/111頁
文件大?。?/td> 1660K
代理商： PC8641MSH1333JB
27
0893C–HIREL–01/10
e2v semiconductors SAS 2010
PC8641 and PC8641D [Preliminary]
.
Notes:
1. LVDD supports eTSECs 1 and 2.
2. TV
DD supports eTSECs 3 and 4.
3. The symbol V
IN, in this case, represents the LVIN and TVIN symbols referenced in Table 3-1 on page 6 and Table 3-2 on page
7.
9.2
FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications
The AC timing specifications for FIFO, GMII, MII, TBI, RGMII, RMII and RTBI are presented in this
section.
9.2.1
FIFO AC Specifications
The basis for the AC specifications for the eTSEC’s FIFO modes is the double data rate RGMII and RTBI
specifications, since they have similar performance and are described in a source-synchronous fashion
like FIFO modes. However, the FIFO interface provides deliberate skew between the transmitted data
and source clock in GMII fashion.
When the eTSEC is configured for FIFO modes, all clocks are supplied from external sources to the rel-
evant eTSEC interface. That is, the transmit clock must be applied to the eTSECn’s TSECn_TX_CLK,
while the receive clock must be applied to pin TSECn_RX_CLK. The eTSEC internally uses the transmit
clock to synchronously generate transmit data and outputs an echoed copy of the transmit clock back
out onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for example). It is
intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a
source- synchronous timing reference. Typically, the clock edge that launched the data can be used,
since the clock is delayed by the eTSEC to allow acceptable set-up margin at the receiver. Note that
there is relationship between the maximum FIFO speed and the platform speed. For more information
Note:
The phase between the output clocks TSEC1_GTX_CLK and TSEC2_GTX_CLK (ports 1 and 2) is no more
than 100 ps. The phase between the output clocks TSEC3_GTX_CLK and TSEC4_GTX_CLK (ports 3 and
4) is no more than 100 ps.
Table 9-2.
GMII, MII, RMII, RGMII, RTBI, TBI and FIFO DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
Notes
Supply voltage 2.5V
LVDD
TVDD
2.375
2.675
V
Output high voltage
(LVDD/TVDD = Min, IOH = -1.0 mA)
V
OH
2LV
DD/TVDD+ 0.3
V
Output low voltage
(LVDD/TVDD = Min, IOL = 1.0 mA)
V
OL
GND - 0.3
0.40
V
Input high voltage
V
IH
1.70
LV
DD/TVDD+ 0.3
V
Input low voltage
V
IL
-0.3
0.70
V
Input high current
(V
IN = LVDD, VIN = TVDD)
I
IH
–10
A
Input low current
(V
IN = GND)
I
IL
-15
–
A
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