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參數(shù)資料
| 型號： | PC8641MSH1333JB |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, CBGA1023 |
| 封裝： | 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023 |
| 文件頁數(shù)： | 49/111頁 |
| 文件大?。?/td> | 1660K |
| 代理商： | PC8641MSH1333JB |
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42
0893C–HIREL–01/10
PC8641 and PC8641D [Preliminary]
e2v semiconductors SAS 2010
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t
(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing
(LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock
one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the out-
put (O) going invalid (X) or output hold time.
2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.
3. All signals are measured from OV
DD/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL
bypass mode to 0.4 × OV
DD of the signal in question for 3.3-V signaling levels.
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
6. tLBOTOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is pro-
grammed with the LBCR[AHD] parameter.
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between comple-
mentary signals at BVDD/2.
8. Guaranteed by design.
Figure 11-1 provides the AC test load for the local bus.
Figure 11-1. Local Bus AC Test Load
Note:
PLL bypass mode is recommended when LBIU frequency is at or below 83 MHz. When LBIU operates
above 83 MHz, LBIU PLL is recommended to be enabled.
Output hold from local bus clock (except LAD/LDP
and LALE)
t
LBKHOX1
0.7
–
ns
Output hold from local bus clock for LAD/LDP
t
LBKHOX2
0.7
–
ns
Local bus clock to output high Impedance (except
LAD/LDP and LALE)
t
LBKHOZ1
–2.5
ns
Local bus clock to output high impedance for
LAD/LDP
t
LBKHOZ2
–2.5
ns
Table 11-2.
Local Bus General Timing Parameters (OV
DD = 3.3V DC) (Continued)
Parameter
Configuration
Symbol(1)
Min
Max
Unit
Notes
BV
DD/2
Output
Z0 = 50Ω
R
L = 50Ω
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