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CHAPTER 7
8-BIT TIMER/EVENT COUNTERS 50, 51
User’s Manual U12790EJ2V0UD
7.4.4 8-bit PWM output operation
The 8-bit timer/event counter can be used for PWM output when bit 6 (TMC5n6) of 8-bit timer mode control register
5n (TMC5n) is set to 1.
A pulse with the duty factor determined by the value set to 8-bit compare register 5n (CR5n) is output from TO5n.
Set the active level width of the PWM pulse to CR5n. The active level is selected by bit 1 (TMC5n) of TMC5n.
The count clock can be selected by bits 0 to 2 (TCL5n0 to TCL5n2) of timer clock select register n (TCL5n).
PWM output can be enabled or disabled by bit 0 (TOE5n) of TMC5n.
Caution
The value of CR5n can be rewritten only once in once cycle in the PWM mode.
Remark
n = 0 or 1
(1) Basic operation of PWM output
[Setting]
<1> Set each register.
Reset the port latches (P130 and P131)Note to “0”.
TCL5n:
Select a count clock.
CR5n:
Set a compare value.
TMC5n:
Select count operation stop, PWM mode, timer output F/F not affected.
TMC5n1
Active level selection
0
Active high
1
Active low
Enable timer output.
(TMC5n = 01000001B or 01000011B)
<2> The count operation is started when TCE5n = 1 is set.
To stop the count operation, set TCE5n to 0.
Note
8-bit timer/event counter 50: P130
8-bit timer/event counter 51: P131
[Operation of PWM output]
<1> When the count operation is started, the PWM output (output from TO5n) remains inactive until an
overflow occurs.
<2> When an overflow occurs, the active level is output. This active level is output until the value of CR5n
matches the count value of 8-bit timer counter 5n (TM5n).
<3> The PWM output remains inactive after CR5n and the count value of TM5n have matched, until an
overflow occurs again.
<4> After that, <2> and <3> are repeated until the count operation is stopped.
<5> When the count operation is stopped because TCE5n is cleared to 0, the PWM output becomes inactive.
Remark
n = 0 or 1