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CHAPTER 17
IEBus CONTROLLER (
PD178096A, 178098A, 178F098 ONLY)
User’s Manual U12790EJ2V0UD
17.4.2 Description of internal registers
The internal registers incorporated in the IEBus controller are described below.
(1) IEBus control register 0 (BCR0)
Figure 17-11. Format of IEBus Control Register 0 (BCR0)
Cautions 1. While the IEBus is operating as the master, writing to the BCR0 register (including bit
manipulation instructions) is disabled until either the end of that communication or frame,
or until communication is stopped by the occurrence of an arbitration-loss communication
error. Master requests cannot therefore be nested. However, if the IEBus is specified as a
slave while a master request is being held pending, the BCR0 register can be written to at
the end of communication to clear the communication end/frame end flag. This is also the
case when communication has been forcibly stopped (ENIEBUS flag = 0).
2. If a bit manipulation instruction for the BCR0 register conflicts with a hardware reset of the
MSTRQ flag, the BCR0 register may not operate normally. The following countermeasures
are recommended in this case.
Because the hardware reset is instigated in the acknowledgment period of the slave
address field, be sure to observe Caution 1 of (b) Master request flag (MSTRQ) below.
Be sure to observe the caution above regarding writing to the BCR0 register.
ENIEBUS
IEBus unit stopped
IEBus unit active
ENIEBUS
0
1
Communication enable flag
BCR0
MSTRQ
ALLRQ ENSLVTX ENSLVRX
00
0
After reset: 00H
R/W
Address: FFB0H
IEBus unit not requested as master
IEBus unit requested as master
MSTRQ
0
1
Master request flag
Individual communication requested
Broadcast communication requested
ALLRQ
0
1
Broadcast request flag
Slave transmission disabled
Slave transmission enabled
ENSLVTX
0
1
Slave transmission enable flag
Slave reception disabled
Slave reception enabled
ENSLVRX
0
1
Slave reception enable flag
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