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CHAPTER 18
INTERRUPT FUNCTIONS
User’s Manual U12790EJ2V0UD
(1) Interrupt request flag registers (IF0L, IF0H, IF1L)
The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction
is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt
request or upon application of reset input.
IF0L, IF0H and IF1L are set by a 1-bit or 8-bit memory manipulation instruction. If IF0L and IF0H are used
as the 16-bit register IF0, use a 16-bit memory manipulation instruction for setting.
Reset input sets these registers to 00H.
Figure 18-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L)
××ID×
Interrupt request flag
0
No interrupt request signal
1
Interrupt request signal is generated;
Interrupt request state
Notes 1. These bits are provided in the
PD178076, 178078, and 178F098 only. Be sure to reset these
bits to 0 in the
PD178096A and 178098A.
2. These bits are provided in the
PD178096A, 178098A, and 178F098 only. Be sure to reset these
bits to 0 in the
PD178076 and 178078.
Cautions 1. The WDTIF flag is R/W enabled only when the watchdog timer is used as an interval timer.
If the watchdog timer is used in watchdog timer mode 1, set the WDTIF flag to 0.
2. To operate the timers, serial interface, and A/D converter after the standby mode has been
released, clear the interrupt request flag, because the interrupt request flag may be set
by noise.
PIF6
SRIF0
Note 1
0
PIF5
SERIF0
Note 1
ADIF
PIF4
TMIF51
IEIF2
Note 2
PIF3
TMIF50
IEIF1
Note 2
PIF2
CSIIF3
TMIF01
PIF1
CSIIF1
TMIF00
PIF0
CSIIF0
BTMIF0
WDTIF
PIF7
STIF0
Note 1
IF0L
IF0H
IF1L
R/W
<0>
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<0>
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<0>
<1>
<2>
<3>
<4>
<5>
<6>
7
After reset
00H
Address
FFE0H
FFE1H
FFE2H
Symbol