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CHAPTER 6
16-BIT TIMER/EVENT COUNTER 0
User’s Manual U12790EJ2V0UD
Figure 6-26. Timing of One-Shot Pulse Output Operation with Software Trigger
Caution
16-bit timer counter 0 (TM0) starts operating as soon as TMC02 and TMC03 are set to values
other than 0, 0 (operation stop mode).
Remark
N < M
(2) One-shot pulse output with external trigger
A one-shot pulse can be output to the TO0/P31 pin by using the valid edge of the TI00/P32 pin as an external
trigger when 16-bit timer mode control register 0 (TMC0), capture/compare control register 0 (CRC0), and 16-
bit timer output control register 0 (TOC0) are set as shown in Figure 6-27.
The rising, falling, or both the rising and falling edges can be selected as the valid edge of the TI00/P32 pin
by bit 4 and 5 (ES00 and ES01) of prescaler mode register 0 (PRM0).
At the valid edge of the TI00/P32 pin, 16-bit timer counter 0 (TM0) is cleared and started, and the output to
TO0/P31 becomes active at the count value written in advance to 16-bit capture/compare register 01 (CR01).
After that, the output becomes inactive at the count value written in advance in 16-bit capture/compare register
00 (CR00)Note.
Note
The case where N < M is described here. When N > M, the output becomes active with the CR00
register and inactive with the CR01 register.
Caution
The external trigger is ignored even if generated while the one-shot pulse is being output.
Count clock
TM0 count value
CR01 set value
CR00 set value
INTTM01
OSPT
INTTM00
TO0 pin output
0000
0001
N
N + 1
0000
N – 1
N
M – 1
M
M + 1
0000
N
M
N
M
N
M
N
M
Set 0CH to TMC0
(TM0 count start)
One-shot pulse