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CHAPTER 21
STANDBY FUNCTION
User’s Manual U12790EJ2V0UD
21.2.2 STOP mode
(1) STOP mode setting and operating status
The STOP mode is set by executing the STOP instruction.
Cautions 1. When the STOP mode is set, the X1 pin is pulled down to GND0, and the X2 pin is internally
pulled up to VDD to minimize the leakage current of the crystal oscillator.
2. Because the interrupt request signal is used to release the standby mode, if there is an
interrupt source with the interrupt request flag set and the interrupt mask flag reset, the
standby mode is immediately released if set. Thus, the STOP mode is reset to the HALT
mode immediately after execution of the STOP instruction, and the operating mode is set
after the wait set using the oscillation stabilization time select register (OSTS).
The operating status in the STOP mode is described below.
Table 21-3. STOP Mode Operating Status
Item
Status
Clock generator
System clock stopped. Clock supply to CPU stopped.
CPU
Stops operating.
Ports
Hold status before STOP mode was set.
16-bit timer/event counter 0
Stop operating and cannot operate.
8-bit timer/event counters 50, 51
Basic timer
Watchdog timer
Buzzer output controller
A/D converter
Serial interface
SIO0, SIO1, SIO3, UART0Note 1
IEBus controllerNote 2
External interrupt
Can operate.
PLL frequency synthesizer
Stop operating and cannot operate.
Frequency counter
Power-on clear circuit
RESET generated when 2.3 V or less is detected.
Notes 1.
PD178076, 178078, and 178F098 only.
2.
PD178096A, 178098A, and 178F098 only.