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CHAPTER 20
FREQUENCY COUNTER
User’s Manual U12790EJ2V0UD
(2) IF counter control register (IFCCR)
This register sets the count start of the IF counter register and clears the IF counter register.
IFCCR is set by a 1-bit or 8-bit memory manipulation instruction.
The value of this register is reset to 00H after reset and in the STOP mode.
In the HALT mode, this register holds the value immediately before the HALT mode was set.
Figure 20-3. Format of IF Counter Control Register (IFCCR)
IFCST
Count start of IF counter register
0
Nothing is affected
1
Counting starts
IFCRES
Clearance of data of IF counter register
0
Nothing is affected
1
Data of IF counter register cleared
Remark
Bits 2 to 7 are fixed to 0 by hardware.
(3) IF counter gate judge register (IFCJG)
This register detects opening/closing of the gate of the frequency counter.
The value of this register is reset to 00H after reset and in the STOP mode.
In the HALT mode, this register holds the value immediately before the HALT mode was set.
Figure 20-4. Format of IF Counter Gate Judge Register (IFCJG)
IFCJG0
Detection of opening/closing of gate of frequency counter
0
Gate is closed
1
 If gate time is set to other than open
Status until gate is closed after IFCST has been set to 1
 If gate time is set to open
Status where gate is open as soon as it has been set to be opened
Remark
Bits 1 to 7 are fixed to 0 by hardware.
Caution
IFCJG0 remains set even if the IF counter register overflows and stops counting, until the
set gate time expires.
7
0
6
0
5
0
4
0
3
0
2
0
IFCST IFCRES
Symbol
IFCCR
R/W
W
After reset
00H
Address
FFACH
<0>
<1>
7
0
6
0
5
0
4
0
3
0
2
0
1
0
IFCJG0
Symbol
IFCJG
R/W
R
After reset
00H
Address
FFABH
<0>