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CHAPTER 20
FREQUENCY COUNTER
User’s Manual U12790EJ2V0UD
20.4 Operation of Frequency Counter
(1) Select the input pin, mode, and gate time by using the IF counter mode select register (IFCMD).
Figure 20-5 shows a block diagram of input pin and mode selection.
(2) Set bit 0 (IFCRES) of the IF counter control register (IFCCR) to 1, and clear the data of the IF counter register.
(3) Set bit 1 (IFCST) of the IF counter control register (IFCCR) to 1.
(4) The gate is opened only for the set gate time from when the 1 kHz internal signal rises after IFCST is set.
If the gate time is set to open, the gate is opened as soon as it has been specified to be opened.
Bit 0 (IFCJG0) of the IF counter gate judge register (IFCJG) is automatically set to 1 as soon as IFCST has
been set to 1.
When the gate time has expired, bit 0 (IFCJG0) of the IF counter gate judge register (IFCJG) is automatically
cleared to 0. If it is specified that the gate be open, however, IFCJG0 is not automatically cleared. In this
case, set a gate time. Figure 20-6 shows the gate timing of the frequency counter.
(5) The IF counter register counts the frequency input to the selected FMIFC or FMIFC pin while the gate is open.
If the FMIFC pin is used in the FMIF count mode, however, the input frequency is divided by half before it
is counted input to the selected FMIFC or AMIFC pin while the gate is open.
The relationship between count value x (decimal), the input frequencies (fFMIFC and fAMIFC), and the gate time (TGATE)
is shown below.
FMIF count mode (FMIFC pin)
fFMIFC =
x
× 2 (kHz)
TGATE
AMIF count mode (FMIFC or AMIFC pin)
fAMIFC =
x
(kHz)
TGATE
Figure 20-5. Block Diagram of Input Pin and Mode Selection
IF counter register
AMP
1/2
AMP
FMIFC
AMIFC
FMIF count mode
AMIF count mode