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CHAPTER 22 RESET FUNCTION
User’s Manual U12790EJ2V0UD
Table 22-1. Hardware Status After Reset (2/3)
Hardware
Status After Reset
Watchdog timer
Clock select register (WDCS)
00H
Mode register (WDTM)
00H
Buzzer output
BEEP0
Frequency select register 0 (BEEPCL0)
00H
controller
BUZ
Clock output control register (CKS)
00H
Serial interface
SIO0
Shift register 0 (SIO0)
Undefined
Slave address register 0 (SVA0)
Undefined
Clock select register 0 (SCL0)
08H
Operating mode register 0 (CSIM0)
00H
Serial bus interface control register 0 (SBIC0)
00H
Interrupt timing specification register 0 (SINT0)
00H
SIO1
Shift register 1 (SIO1)
Undefined
Operating mode register 1 (CSIM1)
00H
Automatic data transmit/receive address pointer register (ADTP)
00H
Automatic data transmit/receive control register (ADTC)
00H
Automatic data transmit/receive transfer interval specification register (ADTI)
00H
SIO3
Shift register 3 (SIO3)
Undefined
Operating mode register 3 (CSIM3)
00H
UART0Note 1
Asynchronous serial interface mode register 0 (ASIM0)
00H
Asynchronous serial interface status register 0 (ASIS0)
00H
Baud rate generator control register 0 (BRGC0)
00H
Transmit shift register 0/receive buffer register 0 (TXS0, RXB0)
FFH
IEBus controllerNote 2
IEBus control register 0 (BCR0)
00H
IEBus unit address register (UAR)
0000H
IEBus slave address register (SAR)
0000H
IEBus other unit address register (PAR)
0000H
IEBus control data register (CDR)
01H
IEBus telegraph length register (DLR)
01H
IEBus data register (DR)
00H
IEBus unit status register (USR)
00H
IEBus interrupt status register (ISR)
00H
IEBus slave status register (SSR)
41H
IEBus communication success counter (SCR)
01H
IEBus transmission counter (CCR)
20H
Notes 1.
PD178076, 178078, and 178F098 only
2.
PD178096A, 178098A, and 178F098 only