
12
User’s Manual U12790EJ2V0UD
CONTENTS
CHAPTER 1 OUTLINE .......................................................................................................................
31
1.1
Features ..............................................................................................................................
31
1.2
Applications .......................................................................................................................
32
1.3
Ordering Information ........................................................................................................
32
1.4
Pin Configuration (Top View) ..........................................................................................
33
1.5
Development of 8-Bit DTS Series ...................................................................................
35
1.6
Block Diagram ...................................................................................................................
36
1.7
Functional Outline ............................................................................................................
39
CHAPTER 2 PIN FUNCTIONS ..........................................................................................................
41
2.1
Pin Function List ...............................................................................................................
41
2.2
Description of Pin Functions ..........................................................................................
44
2.2.1
P00 to P07 (Port 0) ................................................................................................................
44
2.2.2
P10 to P17 (Port 1) ................................................................................................................
44
2.2.3
P20 to P27 (Port 2) ................................................................................................................
44
2.2.4
P30 to P37 (Port 3) ................................................................................................................
45
2.2.5
P40 to P47 (Port 4) ................................................................................................................
45
2.2.6
P50 to P57 (Port 5) ................................................................................................................
46
2.2.7
P60 to P67 (Port 6) ................................................................................................................
46
2.2.8
P70 to P77 (Port 7) ................................................................................................................
46
2.2.9
P100 to P102 (Port 10) .........................................................................................................
46
2.2.10 P120 to P124 (Port 12) .........................................................................................................
47
2.2.11 P130 to P137 (Port 13) .........................................................................................................
47
2.2.12 EO0, EO1 ...............................................................................................................................
47
2.2.13 VCOL, VCOH .........................................................................................................................
47
2.2.14 RESET ....................................................................................................................................
47
2.2.15 X1, X2 .....................................................................................................................................
48
2.2.16 REGOSC ................................................................................................................................48
2.2.17 REGCPU ................................................................................................................................48
2.2.18 VDD ..........................................................................................................................................
48
2.2.19 GND0 to GND2 ......................................................................................................................
48
2.2.20 VDDPORT ................................................................................................................................48
2.2.21 GNDPORT .............................................................................................................................
48
2.2.22 VDDPLL ...................................................................................................................................
48
2.2.23 GNDPLL .................................................................................................................................
48
2.2.24 AVDD .......................................................................................................................................
48
2.2.25 AVSS ........................................................................................................................................
48
2.2.26 VPP (
PD178F098 only) .........................................................................................................
48
2.2.27 IC (Mask ROM versions only) ...............................................................................................
49
2.3
Pin I/O Circuits and Recommended Connection of Unused Pins .............................
50