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CHAPTER 6
16-BIT TIMER/EVENT COUNTER 0
User’s Manual U12790EJ2V0UD
(11) Compare operation
<1>
When a 16-bit timer capture/compare register (CR00/CR01) is overwritten during timer operation, a match
interrupt may be generated or the clear operation may not be performed normally if that value is close to
or larger than the timer value.
<2>
The capture operation may not be performed for CR00/CR01 set to compare mode even if a capture trigger
is input.
(12) Edge detection
<1>
If the TI00 pin or the TI01 pin is high level immediately after system reset and the rising edge or both the
rising and falling edges are specified as the valid edge of the TI00 pin or TI01 pin to enable 16-bit timer
counter 0 (TM0) operation, a rising edge is detected immediately. Be careful when pulling up the TI00 pin
or the TI01 pin. However, the rising edge is not detected at restart after the operation has been stopped.
<2>
The sampling clock used to eliminate noise differs when the TI00 valid edge is used as the count clock
and when it is used as a capture trigger. In the former case, the count clock is fX/23, and in the latter case
the count clock is selected by prescaler mode register 0 (PRM0). The capture operation is not performed
until the valid edge is sampled and the valid level is detected twice, thus eliminating noise with a short pulse
width.
(13) STOP mode setting
Stop the timer operation before setting STOP mode; otherwise the timer may malfunction when the main
system clock starts.