
163
CHAPTER 7
8-BIT TIMER/EVENT COUNTERS 50, 51
User’s Manual U12790EJ2V0UD
7.2 Configuration of 8-Bit Timer/Event Counters 50, 51
8-bit timer/event counters 50 and 51 consist of the following hardware.
Table 7-1. Configuration of 8-Bit Timer/Event Counters 50 and 51
Item
Configuration
Timer counter
8-bit timer counters 50 and 51 (TM50 and TM51)
Register
8-bit compare registers 50 and 51 (CR50 and CR51)
Timer input
TI50, TI51
Timer output
TO50 and TO51
Control registers
Timer clock select registers 50 and 51 (TCL50 and TCL51)
8-bit timer mode control registers 50 and 51 (TMC50 and TMC51)
Port mode register 3 (PM3)
Port 13 (P13)
(1) 8-bit timer counters 50 and 51 (TM50 and TM51)
TM50 and TM51 are 8-bit read-only registers that count the count pulses.
The counter is incremented at the rising edge of the count clock.
When TM50 and TM51 are cascaded and used as a 16-bit timer, their values can be read by using a 16-bit
memory manipulation instruction. However, because TM50 and TM51 are connected by the internal 8-bit bus,
TM50 and TM51 are read separately in this order. Therefore, read the value of TM50 and TM51 when used
as a 16-bit timer twice for comparison, taking changes in the value during counting into consideration.
If the count value is read while the timer is operating, stop input of the count clockNote, and read the count
value at that point.
The count value is cleared to 00H in the following cases.
<1> When RESET is input
<2> When TCE5n is cleared
<3> Upon a match between TM5n and CR5n in the mode in which the timer is cleared and started on a match
between TM5n and CR5n
Note
An error may occur in the count. Select a count clock that has a high/low level longer than two cycles
of the CPU clock.
Caution
In cascade connection mode, the count value is reset to 0000H when TCE50 of the lowest
timer is cleared.
Remark
n = 0, 1