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CHAPTER 6
16-BIT TIMER/EVENT COUNTER 0
User’s Manual U12790EJ2V0UD
(4) Data retention timing of capture register
When a capture trigger is input while a 16-bit capture/compare register (CR00/CR01) is being read, CR00/
CR01 continues the normal capture operation, but the read value at this time is not guaranteed. However,
the interrupt request flag (TMIF00/TMIF01) is set as a result of detecting the valid edge.
Figure 6-34. Data Retention Timing of Capture Register
(5) Setting of valid edge
Set the valid edge of the TI00/P32 pin after clearing bits 2 and 3 (TMC02 and TMC03) of 16-bit timer mode
control register 0 to 0, 0, and stopping the timer operation. The valid edge is specified by using bits 4 and
5 (ES00 and ES01) of prescaler mode register 0 (PRM0).
(6) Re-triggering one-shot pulse
(a) One-shot pulse output with software trigger
Do not set OSPT to 1 while the one-shot pulse is being output. To output the one-shot pulse again, wait
until the INTTM00 interrupt, which occurs on a match between TM0 and CR00, has occurred.
(b) One-shot pulse output with external trigger
The external trigger is ignored even if it is generated again while the one-shot pulse is being output.
(c) One-shot pulse output function
When using the software trigger for one-shot pulse output, fix the level of the TI00/P32 and TI01/P33 pins
to either the high or low level. Otherwise, the external trigger will remain valid even when the software
trigger is used, and the timer will be cleared and started when the level of the TI00/P32 or TI01/P33 pin
changes, resulting in unexpected output of the pulse.
N
X
Capture operation
N + 1
N + 2
M
M + 1
M + 2
TM0 count value
Edge input
Interrupt request flag
Capture read signal
CR01 interrupt value
Count pulse
The read value is not guaranteed.