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CHAPTER 19
PLL FREQUENCY SYNTHESIZER
User’s Manual U12790EJ2V0UD
19.4 Operation of PLL Frequency Synthesizer
19.4.1 Operation of each block of PLL frequency synthesizer
(1) Operation of input select block and programmable divider
The input select block and programmable divider select the input pin and division mode of the PLL frequency
synthesizer and divide the frequency in the selected division mode, according to the setting of the PLL mode
select register (PLLMD).
The programmable counter (12 bits) and pulse swallow counter (5 bits) are binary counters.
The division value (N value) is set to the programmable counter and swallow counter by the PLL data registers
(PLLRL, PLLRH, and PLLR0).
When the N value has been transferred to the programmable counter and swallow counter, frequency division
is performed in the selected division mode according to the status of bit 0 (PLLNS0) of the PLL data transfer
register.
Figure 19-6 shows the configuration of the input select block and programmable divider.
Figure 19-6. Configuration of Input Select Block and Programmable Divider
(2) Operation of reference frequency generator
The reference frequency generator divides the 6.3 MHz or 4.5 MHz output of the crystal resonator and
generates seven types of reference frequency fr for the PLL frequency synthesizer.
Reference frequency fr is selected by the PLL reference mode register (PLLRF).
Figure 19-7 shows the configuration of the reference frequency generator.
PLL
NS0
VCOH
VHF
AMP
HF
MF
VHF
HF
MF
12 bits
Internal bus
PLL data registers
(PLLRL, PLLRH, PLLR0)
5 bits
fN
Two modulus
prescalers
(1/32, 1/33)
Programmable
counter
(12 bits)
Swallow
counter
(5 bits)
VCOL
To -DET
PWM data
transfer register
φ
VCOH
DMD
VCOL
DMD