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CHAPTER 14
SERIAL INTERFACE SIO1
User’s Manual U12790EJ2V0UD
(5) Timing of interrupt request signal generation
The interrupt signal is generated in synchronization with the timing shown in Table 14-2.
Table 14-2. Timing of Interrupt Request Signal Generation
Operating Mode
Timing of Interrupt Request Signal
Single mode
Master mode
10th serial clock at end of transfer
Slave mode
8th serial clock at end of transfer
Repeat transmit mode
Not generated
If bit shift occurs during transmission/reception
8th serial clock
(6) Interval time of automatic transmission/reception
Because read/write to/from the buffer RAM using the automatic transmit/receive function is performed
asynchronously to the CPU processing, the interval time is dependent on the CPU processing at the timing
of the eighth rising of the serial clock and the set value of the automatic data transmit/receive interval
specification register (ADTI). Whether the interval time is dependent on ADTI is selected by setting bit 7
(ADTI7) of ADTI. If ADTI7 is reset to 0, the interval time is 2/fSCK. If ADTI7 is set to 1, the interval time determined
by the set contents of ADTI or the interval time by the CPU processing is selected, whichever is greater.
Figure 14-24 shows the interval time of automatic transmission/reception.
Remark
fSCK: Serial clock frequency
Figure 14-24. Interval Time of Automatic Transmission/Reception
The following expression must be satisfied to access the buffer RAM.
1 transfer cycle
≤ Read access + Write access + CPU buffer RAM access
In the case of a “high-speed CPU & low-speed SCKNote”, the interval time is not necessary. In the case of
a “l(fā)ow-speed CPU & high-speed SCKNote”, the interval time is necessary.
In this case, make sure that a sufficient interval time elapses, by using the automatic data transmit/receive
interval specification register (ADTI), so that the above expression is satisfied.
Note
The speeds of the CPU clock and SCK differ depending on the type of CPU core.
Interval
SCK1
D7
SO1
SI1
CSIIF1
D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0