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CHAPTER 17
IEBus CONTROLLER (
PD178096A, 178098A, 178F098 ONLY)
User’s Manual U12790EJ2V0UD
(10) IEBus slave status register (SSR)
This register indicates the communication status of the slave unit. After receiving a slave status transmission
request from the master, the CPU reads this register, and writes the slave status to the IEBus data register (DR)
to transmit the slave status. At this time, the telegraph length is automatically set to “01H”, so setting of the IEBus
telegraph length register (DLR) is not required (because it is preset by hardware).
Bits 6 and 7 indicate the highest mode supported by the unit, and are fixed to “01H” (mode 1).
Figure 17-25. Format of IEBus Slave Status Register (SSR)
(a) Slave transmission status flag (STATSLV)...Bit 4
Reflects the contents of the slave transmission enable flag.
(b) Lock status flag (STATLOCK)...Bit 2
Reflects the contents of the locked flag.
(c) DR reception status (STATRX)...Bit 1
This flag indicates the DR reception state.
(d) DR transmission status (STATTX)...Bit 0
This flag indicates the DR transmission state.
0
Slave transmission stops
Slave transmission enabled
STATSLV
0
1
Slave transmission status flag
SSR
1
0
STATSLV
0
STATLOCK STATRX
STATTX
Unlock status
Lock status
STATLOCK
0
1
Lock status flag
Receive data not stored in DR
Receive data stored in DR
STATRX
0
1
DR receive status
Transmit data not stored in DR
Transmit data stored in DR
STATTX
0
1
DR transmit status
After reset: 41H
R
Address: FFBDH
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