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CHAPTER 13
SERIAL INTERFACE SIO0
User’s Manual U12790EJ2V0UD
(a) Bus release signal (REL)
The bus release signal occurs when the SB0 (SB1) line changes from low level to high level when the
SCK0 line is high level (without serial clock output).
This signal is output by the master device.
Figure 13-13. Bus Release Signal
The bus release signal indicates that the master device is going to transmit an address to the slave device.
The slave device incorporates hardware to detect the bus release signal.
Caution A transition of the SB0 (SB1) pin from low to high is recognized as a bus release signal
when the SCK0 line is high. If the change timing of the bus is shifted due to the influence
of board capacitance, data that is transmitted may be identified as a bus release signal
by mistake. Exercise care when wiring.
(b) Command signal (CMD)
The command signal occurs when the SB0 (SB1) line changes from high level to low level when the SCK0
line is high level (without serial clock output). This signal is output by the master device.
Figure 13-14. Command Signal
The command signal indicates that the master is going to transmit a command to the slave (however,
the command signal following the bus release signal indicates that an address is to be transmitted).
The slave device incorporates hardware to detect the command signal.
Caution A transition of the SB0 (SB1) pin from high to low is recognized as a command signal
when the SCK0 line is high. If the change timing of the bus is shifted due to the influence
of board capacitance, data that is transmitted may be identified as a command signal
by mistake. Exercise care when wiring.
SCK0
"H"
SB0 (SB1)
SCK0
"H"
SB0 (SB1)