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型號(hào)：	UPD178F098GF-3BA-A
元件分類：	微控制器/微處理器
英文描述：	8-BIT, FLASH, MICROCONTROLLER, PQFP100
封裝：	14 X 20 MM, PLASTIC, QFP-100
文件頁(yè)數(shù)：	296/559頁(yè)
文件大小：	3587K
代理商：	UPD178F098GF-3BA-A

CHAPTER 16

SERIAL INTERFACE UART0 (

PD178076, 178078, AND 178F098 ONLY)

User’s Manual U12790EJ2V0UD

(d) Reception

Reception is enabled when bit 6 (RXE0) of asynchronous serial interface mode register 0 (ASIM0) is set

to 1, and then the input to the RXD0 pin is sampled.

The RXD0 pin is sampled with the serial clock specified by ASIM0.

When the RXD0 pin goes low, the 5-bit counter of the baud rate generator starts counting. When a time

of half the set baud rate has elapsed, the start timing signal of data sampling is output. If the RXD0 pin

is sampled with this start timing signal again and is found to be low level, the pin level is recognized as

a start bit. The 5-bit counter is initialized, counting is started, and the data is sampled. If character data,

a parity bit, and 1 stop bit are detected after the start bit, reception of one frame of data is completed.

When reception of one frame of data has been completed, the receive data in the shift register is

transferred to receive buffer register 0 (RXB0), and a reception completion interrupt request (INTSR0)

is generated.

Even if an error occurs, the receive data in which the error occurred is transferred to RXB0. If bit 1 (ISRM0)

of ASIM0 is cleared to 0 when the error occurred, INTSR0 is generated (refer to Figure 16-10).

INTSR0 is not generated if the ISRM0 bit is set to 1.

If the RXE0 bit is reset to 0 during reception, reception is immediately stopped. At this time, the contents

of RXB0 and ASIS0 are not affected, nor are INTSR0 and INTSER0 generated.

Figure 16-9 shows the timing of generating the reception completion interrupt request of the asynchronous

serial interface.

Figure 16-9. Timing of Generation of Reception Completion Interrupt of Asynchronous Serial Interface

Be sure to read receive buffer register 0 (RXB0) even if a reception error occurs.

Otherwise, an overrun error occurs when the next data is received, and the reception

error status persists.

RXD0 (input)

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