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CHAPTER 17
IEBus CONTROLLER (
PD178096A, 178098A, 178F098 ONLY)
User’s Manual U12790EJ2V0UD
17.6.5 Interval of occurrence of interrupt for IEBus control
Each control interrupt must occur at each point of communication and perform the necessary processing until the next
interrupt occurs. Therefore, the CPU must control the IEBus control block, taking the shortest time of this interrupt into
consideration.
The locations at which the following error interrupts may occur are indicated by
↑ in the field where it may occur. ↑ does
not mean that the interrupt occurs at each of the points indicated by
↑. If an error interrupt (timing error, parity error, NACK
reception, underrun error, or overrun error) occurs, the IEBus internal circuit is initialized. As a result, subsequent
interrupts do not occur in that communication frame.
(1) Master transmission
Figure 17-33. Master Transmission (Interval of Interrupt Occurrence)
Remarks 1. T: Timing error
A: NACK reception
U: Underrun error
: Data set interrupt (INTIE1)
2. End of frame occurs at the end of 32-byte data.
(IEBus: 6.29 MHz operation)
Item
Symbol
MIN.
Unit
Communication starts - timing error
t1
Approx. 93
s
Communication starts - communication start interrupt
t2
Approx. 1,282
s
Communication start interrupt - timing error
t3
Approx. 15
s
Communication start interrupt - end of communication
t4
Approx. 1,012
s
Transmission data request interrupt interval
t5
Approx. 375
s
Start bit
T
t1
T
Broad-
cast
Master address
T
t2
P
Slave address
T
PA
AT
T
t3
Control
P A
A
t4
TA
T
Telegraph
length
P A
Data
P
A
Communication
starts
Communication
start interrupt
PA
Data
A
P
Data
TT
t4
End of communication
End of frame
U
t5
A