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CHAPTER 13
SERIAL INTERFACE SIO0
User’s Manual U12790EJ2V0UD
(b) Serial bus interface control register 0 (SBIC0)
SBIC0 is set by a 1-bit or 8-bit memory manipulation instruction.
Reset input sets SBIC0 to 00H.
R/W
RELT
Use for stop condition signal output. When RELT = 1, SO latch is set to 1. After SO latch setting,
automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
R/W
CMDT
Use for start condition signal output. When CMDT = 1, SO latch is cleared to 0. After clearing SO latch,
automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
R
RELD
Detection of stop condition
Clear conditions (RELD = 0)
Setting conditions (RELD = 1)
 When transfer start instruction is executed
 When stop condition is detected
 If SIO0 and SVA0 values do not match in address reception
 When CSIE0 = 0
 When reset input is applied
R
CMDD
Detects Start condition
Clear conditions (CMDD = 0)
Setting conditions (CMDD = 1)
 When transfer start instruction is executed
 When start condition is detected
 When stop condition is detected
 When CSIE0 = 0
 When reset input is applied
R/W
ACKT
SDA0 (SDA1) is set to low level after the instruction to be set to 1 is executed (ACKT = 1) before the next
SCL falling edge. Used for generating an ACK signal by software if the 8-clock wait mode is selected.
Cleared to 0 if CSIE = 0 when a transfer by the serial interface is started.
(Continued)
Note
Bits 2, 3, and 6 (RELD, CMDD, ACKD) are read-only bits.
<6>
<5>
<4>
<3>
<2>
<1>
<0>
<7>
Symbol
SBIC0
BSYE ACKD ACKE
FF61H
00H
R/W Note
Address
After reset
R/W
ACKT CMDD RELD CMDT RELT