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CHAPTER 14
SERIAL INTERFACE SIO1
User’s Manual U12790EJ2V0UD
(d) Bit shift detection by busy signal
During automatic transmission/reception, a bit shift of the serial clock of the slave device may occur
because noise is superimposed on the serial clock signal output by the master device. Unless the strobe
control option is used at this time, the bit shift affects transmission of the next byte. In this case, the master
can detect the bit shift by checking the busy signal during transmission by using the busy control option.
A bit shift is detected by using the busy signal as follows.
The slave outputs the busy signal after the rising of the eighth serial clock during data transmission/
reception (to not keep transmission/reception waiting by the busy signal at this time, make the busy signal
inactive within 2 clocks).
The master samples the busy signal in synchronization with the falling of the leading side of the serial
clock. If a bit shift has not occurred, all the eight serial clocks that have been sampled are inactive. If
the sampled serial clocks are active, it is assumed that a bit shift has occurred, and error processing is
executed (by setting bit 4 (ERR) of the automatic transmit/receive control register (ADTC) to 1).
Figure 14-23 shows the operation timing of the bit shift detection function by the busy signal.
Figure 14-23. Operation Timing of Bit Shift Detection Function by Busy Signal (When BUSY0 = 1)
CSIIF1: Interrupt request flag
CSIE1: Bit 7 of serial operating mode register 1 (CSIM1)
ERR:
Bit 4 of the automatic data transmit/receive control register (ADTC)
SCK1
(slave)
D7
SO1
SI1
D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1
D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1
D0
BUSY
CSIIF1
CSIE1
ERR
D7
Busy not detected
Error interrupt request
generated
Error detected
Bit shift due to noise
SCK1
(master)