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CHAPTER 11
A/D CONVERTER
User’s Manual U12790EJ2V0UD
11.4 A/D Converter Operations
11.4.1 Basic operations of A/D converter
(1) Select one channel for A/D conversion using A/D converter analog input channel specification register 3
(ADS3).
(2) Sample the voltage input to the selected analog input channel using the sample & hold circuit.
(3) Sampling for the specified period of time sets the sample & hold circuit to the hold state so that the circuit
holds the input analog voltage until the end of A/D conversion.
(4) Bit 7 of the successive approximation register (SAR) is set and the tap selector sets the series resistor string
voltage tap to (1/2) AVDD.
(5) The voltage difference between the series resistor string voltage tap and analog input is compared by a voltage
comparator. If the analog input is greater than (1/2) AVDD, the MSB of SAR remains set. If the input is smaller
than (1/2) AVDD, the MSB is reset.
(6) Next, bit 6 of SAR is automatically set and the operation proceeds to the next comparison. In this case, the
series resistor string voltage tap is selected according to the preset value of bit 7 as described below.
 Bit 7 = 1: (3/4) AVDD
 Bit 7 = 0: (1/4) AVDD
The voltage tap and analog input voltage are compared and bit 6 of SAR is manipulated with the result as
follows.
 Analog input voltage
≥ Voltage tap: Bit 6 = 1
 Analog input voltage < Voltage tap: Bit 6 = 0
(7) Comparison of this sort continues up to bit 0 of SAR.
(8) Upon completion of the comparison of 8 bits, an effective digital resultant value remains in SAR and the
resultant value is transferred to and latched in A/D conversion result register 3 (ADCR3).
At the same time, the A/D conversion end interrupt request (INTAD) can also be generated.
Caution
The value immediately after A/D conversion has been started is undefined.
Take appropriate measures, such as discarding the first conversion result by polling the
A/D conversion end interrupt request (INTAD).