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CHAPTER 13
SERIAL INTERFACE SIO0
User’s Manual U12790EJ2V0UD
(2) Serial operating mode register 0 (CSIM0)
This register sets the serial interface SIO0 serial clock, operating mode, operation enable/stop, and wakeup
function, and displays the address comparator match signal.
CSIM0 is set by a 1-bit or 8-bit memory manipulation instruction.
Reset input sets CSIM0 to 00H.
Caution
Do not change the operating mode (3-wire serial I/O, 2-wire serial I/O, or SBI) while the
operation of serial interface SIO0 is enabled. To change the operating mode, stop the serial
operation.
Figure 13-5. Format of Serial Operating Mode Register 0 (CSIM0) (1/2)
(Continued)
Caution
When using SCK0 or SCL, set P27 to 1. If P27 is set to 0, it always outputs a low level.
Notes 1. Bit 6 (COI) is a read-only bit.
2. Can be used as P25 (CMOS input/output) when used only for transmission.
3. Can be used freely as a port function.
Remark
×:
Don’t care
PM
××: Port mode register
P
××:
Output latch of port
SBI mode
<6>
<5>
4
3210
<7>
Symbol
CSIM0
CSIE0 COI
WUP CSIM04 CSIM03 CSIM02 CSIM01
0
CSIM01
0
Selection of serial interface SIO0 clock
Input clock to SCK0/SCL/P27 pin from off-chip
0
SCK0
(CMOS I/O)
R/W
1
Clock specified by bits 0 to 3 of serial interface clock select register 0 (SCL0)
CSIM
04
0
1
FF60H
00H
R/WNote 1
Address
After reset
R/W
CSIM
03
CSIM
02
PM25 P25 PM26 P26 PM27 P27
Operating
mode
Start bit
SIO/SB0/SDA0/P25
pin function
SO0/SB1/SDA1/P26
pin function
SCK0/SCL/P27
pin function
×
10
×
0
×
0
×
0
×
0
1
Note 3 Note 3
MSB
P25
(CMOS I/O)
SB0
(N-ch open-
drain I/O)
SB1
(N-ch open-
drain I/O)
P26
(CMOS I/O)
1
MSB
LSB
1
×
0001
Note 2
3-wire serial
l/O mode
SI0Note 2
(Input)
SO0
(CMOS output)
SCK0
(CMOS I/O)
2-wire serial
l/O mode
or
I2C bus
mode
0
SCK0/SCL
(N-ch open-
drain I/O)
1
11
×
0
×
0
×
0
×
0
1
Note 3 Note 3
MSB
P25
(CMOS I/O)
SB0/SDA0
(N-ch open-
drain I/O)
SB1/SDA1
(N-ch open-
drain I/O)
P26
(CMOS I/O)
Note 2