
559
APPENDIX C REVISION HISTORY
User’s Manual U12790EJ2V0UD
(2/2)
Edition
Revision
Chapter
2nd
Addition of Caution about inversion of IEBus protocol and signal inside the
CHAPTER 17 IEBus
microcontroller to 17.1.6 Transfer format of IEBus and 17.1.8 Bit format
CONTROLLER
Modification of Note and Caution in 17.1.6 (9) Acknowledge bit
(
PD178096A,178098A,
Addition of description of lock setting conditions and lock release conditions to
178F098 ONLY)
17.1.7 (4) Locking and unlocking
Addition of description of timing error detection for each period to 17.1.8 Bit format
Addition of Notes about automatic master reprocessing to Table 17-7 Comparison
of Existing and Simple IEBus Interface Functions
17.4.2 Description of internal registers
Explanation of each register thoroughly modified and Note added
Addition of figures of interrupt timing to Figures 17-16 to 17-19
Addition of Figure 17-23 Example of Broadcast Communication Flag
Operation
Addition of Table 17-9 Reset Conditions of Flags in ISR Register
17.5 Interrupt Operations of IEBus Controller
Thorough modification of contents
Addition of 17.5.3 Communication error source processing list
Addition of description of wait of slave unit to 17.6.2 Master reception
Correction of description of drive type of EO1 pin in 19.4.1 Operation of each
CHAPTER 19 PLL
block of PLL frequency synthesizer
FREQUENCY
SYNTHESIZER
Correction of Note in Table 22-1 Hardware Status After Reset
CHAPTER 22 RESET
FUNCTION
Thorough modification of descriptions of flash memory programming as 23.3 Flash
CHAPTER 23
Memory Features
PD178F098
Addition of chapters
CHAPTER 25
ELECTRICAL
SPECIFICATIONS
CHAPTER 26
PACKAGE DRAWING
CHAPTER 27
RECOMMENDED
SOLDERING
CONDITIONS
Thorough modification of descriptions of development tools
APPENDIX A
Deletion of EMBEDDED SOFTWARE
DEVELOPMENT
TOOLS
Addition of chapters
APPENDIX B
REGISTER INDEX
APPENDIX C
REVISION HISTORY