
22
User’s Manual U12790EJ2V0UD
7-3
Format of Timer Clock Select Register 50 (TCL50) ..........................................................................
165
7-4
Format of Timer Clock Select Register 51 (TCL51) ..........................................................................
166
7-5
Format of 8-Bit Timer Mode Control Register 50 (TMC50) ..............................................................
167
7-6
Format of 8-Bit Timer Mode Control Register 51 (TMC51) ..............................................................
168
7-7
Format of Port Mode Register 3 (PM3) .............................................................................................
169
7-8
Timing of Interval Timer Operation ....................................................................................................
171
7-9
Operation Timing of External Event Counter (with Rising Edge Specified) .....................................
174
7-10
Timing of Square-Wave Output Operation ........................................................................................
175
7-11
Operation Timing of PWM Output ......................................................................................................
177
7-12
Timing of Operation When CR5n Is Changed ...................................................................................
178
7-13
16-Bit Cascade Connection Mode .....................................................................................................
180
7-14
Start Timing of 8-Bit Timer Counter 5n ..............................................................................................
184
8-1
Block Diagram of Basic Timer ............................................................................................................
185
8-2
Timing of Basic Timer Operation .......................................................................................................
186
8-3
Operation Timing to Poll BTMIF0 Flag ..............................................................................................
186
9-1
Block Diagram of Watchdog Timer ....................................................................................................
187
9-2
Format of Watchdog Timer Clock Select Register (WDCS) .............................................................
190
9-3
Format of Watchdog Timer Mode Register (WDTM) ........................................................................
191
10-1
Block Diagram of BEEP0 ....................................................................................................................
194
10-2
Block Diagram of BUZ ........................................................................................................................
194
10-3
Format of BEEP Frequency Select Register 0 (BEEPCL0) ..............................................................
196
10-4
Format of Clock Output Select Register (CKS) .................................................................................
196
11-1
Block Diagram of A/D Converter ........................................................................................................
199
11-2
Format of A/D Converter Mode Register 3 (ADM3) ..........................................................................
202
11-3
Format of Analog Input Channel Specification Register 3 (ADS3) ..................................................
203
11-4
Format of Power-Fail Comparison Mode Register 3 (PFM3) ...........................................................
204
11-5
Basic Operation of A/D Converter ......................................................................................................
206
11-6
Relationship Between Analog Input Voltage and A/D Conversion Result .......................................
207
11-7
A/D Conversion Operation ..................................................................................................................
209
11-8
Power-Fail Comparison Threshold Value Register 3 (PFT3) ...........................................................
210
11-9
A/D Conversion Operation in Power-Fail Comparison Mode ...........................................................
211
11-10
Circuit Configuration of Series Resistor String ..................................................................................
214
11-11
Analog Input Pin Handling ..................................................................................................................
215
11-12
A/D Conversion End Interrupt Request Generation Timing ..............................................................
216
13-1
System Configuration Example of Serial Bus Interface (SBI) ..........................................................
219
13-2
Serial Bus Configuration Example Using I2C Bus .............................................................................
220
13-3
Block Diagram of Serial Interface SIO0 .............................................................................................
222
13-4
Format of Serial Interface Clock Select Register 0 (SCL0) ..............................................................
226
LIST OF FIGURES (3/8)
Figure No.
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