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CHAPTER 6
16-BIT TIMER/EVENT COUNTER 0
User’s Manual U12790EJ2V0UD
6.4.6 PPG output operation
16-bit timer/event counter 0 operates as a PPG (Programmable Pulse Generator) output when 16-bit timer mode
control register 0 (TMC0) and capture/compare control register 0 (CRC0) are set as shown in Figure 6-29.
The PPG output pulse is a square wave and is output from the TO0/P31 pin. One cycle of this pulse is specified
by the count value preset to 16-bit capture/compare register 00 (CR00), and the pulse width is specified by the count
value preset to 16-bit capture/compare register 01 (CR01).
Figure 6-29. Setting of Control Register for PPG Output Operation
(a) 16-bit timer mode control register 0 (TMC0)
(b) Capture/compare control register 0 (CRC0)
(c) 16-bit timer output control register 0 (TOC0)
Cautions 1. Set CR00 and CR01 to a value in the following range.
0000H < CR01 < CR00
≤ FFFFH
2. The cycle of the pulse generated by PPG output is (set value of CR00 + 1), and the duty factor
is (set value of CR01 + 1)/(set value of CR00 + 1).
Remark
×: Don’t care
00000
CRC02
0
CRC01
×
CRC00
0
CRC0
CR00 is used as compare register.
CR01 is used as compare register.
0000
TMC03
1
TMC02
1
TMC01
0
OVF0
0
TMC0
Clear & start on match between
TM0 and CR00
0
OSPT
0
OSPE
0
TOC04
1
LVS0
0/1
LVR0
0/1
TOC01
1
TOE0
1
TOC0
TOC output enabled
Output inverted on match between TM0 and CR00
Specification of initial value of TO0 output F/F
Output inverted on match between TM0 and CR01
One-shot pulse output disabled