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CHAPTER 21
STANDBY FUNCTION
User’s Manual U12790EJ2V0UD
21.2 Standby Function Operations
21.2.1 HALT mode
(1) HALT mode setting and operating status
The HALT mode is set by executing the HALT instruction.
The operating status in the HALT mode is described below.
Table 21-1. HALT Mode Operating Status
Item
Status
Clock generator
System clock oscillates. Clock supply to CPU stopped.
CPU
Stops operating.
Port
Hold status before HALT mode was set.
16-bit timer/event counter 0
Hold operation before HALT mode was set and can operate.
8-bit timer/event counters 50, 51
Basic timer
Watchdog timer
Buzzer output controller
A/D converter
Holds operation performed when HALT mode was set.
However, comparison cannot be performed correctly in A/D conversion operation mode.
In power-fail comparison mode, operation is as follows depending on setting of bit 5
(PFHRM3) of power-fail comparison mode register 3 (PFM3):
PFHRM3 = 0: Comparison cannot be performed normally.
PFHRM3 = 1: Power-fail comparison operation can be performed.
Serial interface
SIO0, SIO3,
Hold operation performed when HALT mode was set and can operate.
UART0Note 1
SIO1
Holds operation performed when HALT mode was set.
However, transfer is continued with erroneous data if serial clock is supplied in automatic
transfer mode.
IEBus controllerNote 2
Hold operation before HALT mode was set and can operate.
External interrupt
PLL frequency synthesizer
Frequency counter
Holds operation performed before HALT mode was set.
However, operation is not performed correctly even though it is continued.
Power-on clear circuit
Reset when voltage of less than 3.5 V is detected.
Notes 1.
PD178076, 178078, and 178F098 only.
2.
PD178096A, 178098A, and 178F098 only.