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型號(hào)：	UPD178F098GF-3BA-A
元件分類：	微控制器/微處理器
英文描述：	8-BIT, FLASH, MICROCONTROLLER, PQFP100
封裝：	14 X 20 MM, PLASTIC, QFP-100
文件頁(yè)數(shù)：	148/559頁(yè)
文件大小：	3587K
代理商：	UPD178F098GF-3BA-A

CHAPTER 13

SERIAL INTERFACE SIO0

User’s Manual U12790EJ2V0UD

Figure 13-6. Format of Serial Bus Interface Control Register 0 (SBIC0) (3/3)

(b) I2C bus mode

Notes 1. This setting should be performed before transfer.

2. If 8-clock wait mode is selected, the acknowledge signal at reception must be output using ACKT.

3. The busy mode can be canceled by the start of serial interface transfer or the reception of an

address signal. However, the BSYE flag is not cleared to 0.

4. When using the wakeup function, be sure to set BSYE to 1.

CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)

Control of acknowledge signal outputNote 1

Acknowledge signal automatic output disabled. (However, output with ACKT is enabled)

Used for reception when 8-clock wait mode is selected or for transmission. Note 2

Acknowledge signal automatic output enabled.

Acknowledge signal output in synchronization with the falling edge of the 9th SCL clock cycle

(automatically output when ACKE = 1).

However, not automatically cleared to 0 after acknowledge signal output.

Used in reception with 9-clock wait mode selected.

Detection of acknowledge

Clear conditions (ACKD = 0)

When transfer start instruction is executed

When CSIE0 = 0

When reset input is applied

Set conditions (ACKD = 1)

When acknowledge signal (ACK) is detected at the

rising edge of SCL clock after completion of

Control of N-ch open-drain output for transmission in I2C bus modeNote 4

Output enabled (transmission)

Output disabled (reception)

SDA0 (SDA1) is set to low just after execution of the instruction to be set to 1 before the next SCL falling

edge. Used for generating an ACK signal by software if the 8-clock wait mode is selected. Cleared

to 0 if CSIE = 0 when a transfer by the serial interface is started.

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