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CHAPTER 13
SERIAL INTERFACE SIO0
User’s Manual U12790EJ2V0UD
(3) Serial bus interface control register 0 (SBIC0)
This register sets the serial bus interface SIO0 operation and display the status.
SBIC0 is set by a 1-bit or 8-bit memory manipulation instruction.
Reset input sets SBIC0 to 00H.
Figure 13-6. Format of Serial Bus Interface Control Register 0 (SBIC0) (1/3)
Note
Bits 2, 3, and 6 (RELD, CMDD and ACKD) are read-only bits.
Remarks 1. Bits 0, 1, and 4 (RELD, CMDT, and ACKT) are 0 when read after data setting.
2. CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
<6>
<5>
<4>
<3>
<2>
<1>
<0>
<7>
Symbol
SBIC0
BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
RELT
Used for bus release signal output in SBI mode and stop condition signal output.
When RELT = 1, SO Iatch is set to 1. After SO latch setting, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
R/W
FF61H
00H
R/WNote
Address
After reset
R/W
CMDT
Used for command signal output in SBI mode and start condition signal output.
When CMDT = 1, SO Iatch is cleared to (0). After SO latch clearance, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
R/W
R
RELD
Detection of bus release (SBI mode)/stop condition (I2C bus mode)
Set conditions (RELD =1)
Clear conditions (RELD = 0)
 When bus release signal (REL) or stop condition
is detected
 When transfer start instruction is executed
 If SIO0 and SVA0 values do not match in
address reception
 When CSIE0 = 0
 When reset input is applied
R
CMDD
Detection of command (SBI mode)/start condition (I2C bus mode)
Clear conditions (CMDD = 0)
 When transfer start instruction is executed
 When bus release signal (REL) or stop condition is
detected
 When CSIE0 = 0
 When reset input is applied
Set conditions (CMDD = 1)
 When command signal (CMD) or stop condition
is detected