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型號(hào)：	UPD178F098GF-3BA-A
元件分類：	微控制器/微處理器
英文描述：	8-BIT, FLASH, MICROCONTROLLER, PQFP100
封裝：	14 X 20 MM, PLASTIC, QFP-100
文件頁(yè)數(shù)：	140/559頁(yè)
文件大小：	3587K
代理商：	UPD178F098GF-3BA-A

CHAPTER 13

SERIAL INTERFACE SIO0

User’s Manual U12790EJ2V0UD

(3) SO0 latch

This latch holds the SI0/SB0/SDA0/P25 and SO0/SB1/SDA1/P26 pin levels. It can be directly controlled by

software. In the SBI mode, this latch is set at the end of the 8th serial clock.

(4) Serial clock counter

This counter counts the serial clocks to be output and input during transmission/reception and to check whether

8-bit data has been transmitted/received.

(5) Serial clock controller

This circuit controls serial clock supply to serial I/O shift register 0 (SIO0). When the internal system clock

is used, this circuit also controls clock output to the SCK0/SCL/P27 pin.

(6) Interrupt request signal generator

This circuit controls interrupt request signal generation. It generates an interrupt request signal in the following

In the 3-wire serial I/O mode and 2-wire serial I/O mode

This circuit generates an interrupt request signal every eight serial clocks.

In the SBI mode

When WUPNote is 0 ........ Generates an interrupt request signal every eight serial clocks.

When WUPNote is 1 ........ Generates an interrupt request signal when the serial I/O shift register 0 (SIO0)

value matches the slave address register 0 (SVA0) value after address reception.

WUP is the wakeup function specification bit. It is bit 5 of serial operating mode register 0 (CSIM0).

In the I2C bus mode

Generates an interrupt request as shown in Table 13-2.

(7) Output circuit and detector of control signals

These two circuits output and detect various control signals in the SBI mode.

They do not operate in the 3-wire serial I/O mode and 2-wire serial I/O mode.

In the SBI mode

Busy/acknowledge output circuit, bus release/command/acknowledge detector

In the I2C bus mode

Acknowledge output circuit, stop condition/start condition/acknowledge detector

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