
PRELIMINARY
97
A
82453KX/GX, 82452KX/GX, 82451KX/GX (MC)
Table 10. DC/DP Interchip Signals (DP)
Signal
Type
Description
MEMCMD[7:0]#
I/O
CMOS
MEMORY SIDE COMMAND. These signals transfer command and configu-
ration information between the DC and DP.
MEMERR[1:0]#
O
CMOS
MEMORY ERROR. These signals transfer memory error information from the
DP to the DC.
SYSCMD[4:0]#
I
CMOS
SYSTEM SIDE COMMAND. These signals send commands and other
information from the DC to the DP.
SYSDEN#
I
CMOS
SYSTEM SIDE DATA ENABLE. This signal permits the DC to control the
enabling of DP data information onto the host bus.
SYSERR#
O
CMOS
SYSTEM ERROR. This signal sends system error data conditions from the DP
to the DC.
Table 11. Clock, Power, Reset Signal (DP)
Signal
Type
Description
BCLK
I
CMOS
BUS CLOCK. This is the clock input for the DP.
GTLREFV
I
Analog
GTL REFERENCE VOLTAGE. GTLREFV sets the voltage level used by the GTL
input receivers for comparison against incoming GTL level signals.
MIRST#
I
CMOS
MEMORY INTERFACE RESET. This signal is driven by MIRST# signal from the DC.
Table 12. Test Signals (DP)
Signal
Type
Description
TCK
I
CMOS
JTAG Test Clock. When TMS is tied low, this signal has no effect on normal
operation.
TDI
I
CMOS
JTAG Test Data In. When TMS is tied low, this signal has no effect on normal
operation.
TDO
O
CMOS
JTAG Test Data Out. When TMS is tied low, this signal has no effect on normal
operation.
TESTHI
I/O
TEST HIGH. These signals must be tied high using a 10K
resistor for proper
operation in both test and normal operating modes.
TESTLO
I/O
TEST LOW. These signals must be tied low using a 1K
resistor for proper
operation in both test and normal operating modes.
TMS
I
CMOS
JTAG Test Mode Select. This signal must be tied low for normal operation.
TRST#
I
CMOS
JTAG Test Reset. When TMS is tied low, this signal has no effect on normal
operation.